公开(公告)号：US20140361359A1

公开(公告)日：2014-12-11

申请号：US13914641

申请日：2013-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Sheng Yang ,  Chien-Hung Chen

IPC: H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer.

Abstract translation: 公开了一种氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）器件。 SONOS器件包括衬底; 衬底上的第一氧化物层; 在所述第一氧化物层上的富硅捕获层; 富硅捕获层上的含氮层; 含氮层上的富硅氧化物层; 和富硅氧化物层上的多晶硅层。

公开(公告)号：US08848454B2

公开(公告)日：2014-09-30

申请号：US13633732

申请日：2012-10-02

Applicant: United Microelectronics Corp.

Inventor： Feng-Ji Tsai ,  Shen-De Wang ,  Wen-Chung Chang ,  Ya-Huei Huang ,  Chien-Hung Chen

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/26 ,  H01L29/4234 ,  H01L29/42348 ,  H01L29/7923

Abstract: A method for programming a non-volatile memory cell is described. The memory cell includes a substrate, a gate over the substrate, a charge-trapping structure at least between the substrate and the gate, and first and second S/D regions in the substrate beside the gate. The method includes performing a channel-initiated secondary electron (CHISEL) injection process to inject electrons to the charge-trapping structure.

Abstract translation: 描述用于编程非易失性存储器单元的方法。 存储单元包括衬底，衬底上的栅极，至少在衬底和栅极之间的电荷捕获结构以及栅极旁边的衬底中的第一和第二S / D区域。 该方法包括执行通道引发的二次电子（CHISEL）注入过程以将电子注入电荷捕获结构。

公开(公告)号：US20140175531A1

公开(公告)日：2014-06-26

申请号：US13723159

申请日：2012-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Huei Huang ,  Shen-De Wang ,  Wen-Chung Chang ,  Feng-Ji Tsai ,  Chien-Hung Chen

IPC: H01L29/66 ,  H01L29/792

CPC classification number: H01L29/66833 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/792

Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.

Abstract translation: 一种用于制造非易失性存储结构的方法包括提供具有栅极结构的衬底，执行第一氧化工艺以形成至少覆盖导电层的底角的第一SiO层，执行第一蚀刻工艺以除去第一 SiO层和所述电介质层的一部分以形成空腔，执行第二氧化工艺以形成覆盖所述空腔的侧壁的第二SiO层和覆盖所述衬底的表面的第三SiO层，形成填充在所述腔中的第一SiN层 并且覆盖衬底上的栅极结构，并且去除第一SiN层的一部分以形成SiN结构，其包括填充在空腔中的脚部和从脚部向上延伸的勃起部，以及覆盖侧壁的安装部 门结构。

公开(公告)号：US20230090612A1

公开(公告)日：2023-03-23

申请号：US17991765

申请日：2022-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chun-Hsien Lin ,  Chien-Hung Chen

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/45

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

公开(公告)号：US20210217866A1

公开(公告)日：2021-07-15

申请号：US16793930

申请日：2020-02-18

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Jen Yang Hsueh ,  Ling Hsiu Chou ,  Chih-Yang Hsu

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/51 ,  H01L21/762 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788

Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.

公开(公告)号：US10559573B2

公开(公告)日：2020-02-11

申请号：US16162340

申请日：2018-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Ru Wang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chien-Hung Chen ,  Chun-Hsien Huang ,  Li-Ping Huang ,  Chun-Yen Tseng ,  Meng-Ping Chuang

IPC: H01L27/11 ,  G11C11/412 ,  G11C5/06 ,  G11C8/14 ,  G11C7/18 ,  H01L27/02 ,  H01L27/12 ,  H01L27/092

Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.

公开(公告)号：US20190096892A1

公开(公告)日：2019-03-28

申请号：US16162340

申请日：2018-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Ru Wang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chien-Hung Chen ,  Chun-Hsien Huang ,  Li-Ping Huang ,  Chun-Yen Tseng ,  Meng-Ping Chuang

IPC: H01L27/11 ,  G11C11/412 ,  G11C7/18 ,  G11C8/14 ,  G11C5/06

Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.

公开(公告)号：US20190087481A1

公开(公告)日：2019-03-21

申请号：US15820662

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chin Wang ,  Ya-Ching Cheng ,  Chien-Hung Chen ,  Chun-Liang Hou ,  Da-Ching Liao

IPC: G06F17/30 ,  G05B19/418

CPC classification number: G06F16/285 ,  G05B19/4183 ,  G05B2219/31318

Abstract: A manufacture parameters grouping and analyzing method, and a manufacture parameters grouping and analyzing system are provided. The manufacture parameters grouping and analyzing method includes the following steps: A plurality of process factors are classified into a plurality of groups. In each of the groups, an intervening relationship between any two of the process factors is larger than a predetermined correlation value. In each of the groups, at least one representative factor is selected from each of the groups according to a plurality of outputting relationships of the process factors related to an output factor or a plurality of sample amounts of the process factors. Finally, the representative factor is used for various applications.

公开(公告)号：US10153287B1

公开(公告)日：2018-12-11

申请号：US15795247

申请日：2017-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Ru Wang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chien-Hung Chen ,  Chun-Hsien Huang ,  Li-Ping Huang ,  Chun-Yen Tseng ,  Meng-Ping Chuang

IPC: H01L27/11 ,  H01L27/02 ,  H01L29/78 ,  H01L23/528 ,  H01L21/3213 ,  H01L23/522 ,  H01L21/8238 ,  H01L27/092

Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise an identical first fin structure, the PG2A and the PG2B comprise an identical second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2.

公开(公告)号：US20180286872A1

公开(公告)日：2018-10-04

申请号：US15498464

申请日：2017-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Meng-Ping Chuang ,  Hsueh-Hao Shih

IPC: H01L27/11 ,  H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  G11C11/417

Abstract: A semiconductor memory device having a memory cell including a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions, a plurality of second regions, a plurality of third regions, and a plurality of fourth regions, and each first region includes the memory cell. Each second region, each third region and each fourth region include a voltage contact to provide a voltage to the first P-type well region, the second P-type well region, and the N-type well region. The first region to the fourth region do not overlap with each other.