公开(公告)号：US20140332824A1

公开(公告)日：2014-11-13

申请号：US14340267

申请日：2014-07-24

Applicant: United Microelectronics Corp.

Inventor： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Chih-Chien Liu

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/16 ,  H01L29/10 ,  H01L29/161

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/3141 ,  H01L21/3185 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/10879 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

Abstract: A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height.

Abstract translation: 描述用于形成FinFET的半导体结构。 半导体结构包括半导体衬底，衬底上的FinFET的多个奇数鳍片，以及FinFET的奇数鳍片之间的衬底上的FinFET的多个偶数鳍片。 FinFET的奇数鳍从衬底定义。 FinFET的均匀鳍片与宽度和材料中的至少一个中的FinFET的奇数鳍不同，并且可以与FinFET的高度的奇数鳍不同。

公开(公告)号：US10790289B2

公开(公告)日：2020-09-29

申请号：US16583272

申请日：2019-09-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Po-Chun Chen ,  Chia-Lung Chang

IPC: H01L21/00 ,  H01L27/108 ,  H01L21/02 ,  H01L21/8234

Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.

公开(公告)号：US10651040B2

公开(公告)日：2020-05-12

申请号：US15986797

申请日：2018-05-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Hao Liu ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Po-Chih Wu ,  Pin-Hong Chen ,  Chun-Chieh Chiu ,  Tzu-Chieh Chen ,  Chih-Chien Liu ,  Chih-Chieh Tsai ,  Ji-Min Lin

IPC: H01L21/28 ,  G11C11/4097 ,  H01L27/108

Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.

公开(公告)号：US20190319031A1

公开(公告)日：2019-10-17

申请号：US15972216

申请日：2018-05-06

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Yi-Wei Chen ,  Chun-Chieh Chiu ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Chih-Chien Liu

IPC: H01L27/108 ,  H01L21/285 ,  H01L21/28 ,  H01L21/22

Abstract: The present invention provides a bit line gate structure comprising a substrate, an amorphous silicon layer disposed on the substrate, a first doped region located in the amorphous silicon layer, a titanium silicon nitride (TiSiN) layer, located in the amorphous silicon layer, and a second doped region located in the TiSiN layer, the first doped region contacts the second doped region directly.

公开(公告)号：US20190249297A1

公开(公告)日：2019-08-15

申请号：US15919191

申请日：2018-03-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chien Liu ,  Pin-Hong Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen

IPC: C23C16/455 ,  H01L21/768 ,  H01L23/544 ,  H01L21/285 ,  H01L21/321 ,  C23C16/02 ,  C23C16/34

Abstract: A semiconductor device includes a substrate, a dielectric layer, a first tungsten layer, an interface layer and a second tungsten layer. The dielectric layer is disposed on the substrate and has a first opening and a second opening larger than the first opening. The first tungsten layer is filled in the first opening and is disposed in the second opening. The second tungsten layer is disposed on the first tungsten layer in the second opening, wherein the second tungsten layer has a grain size gradually increased from a bottom surface to a top surface. The interface layer is disposed between the first tungsten layer and the second tungsten layer, wherein the interface layer comprises a nitrogen containing layer. The present invention further includes a method of forming a semiconductor device.

公开(公告)号：US09923095B2

公开(公告)日：2018-03-20

申请号：US15379486

申请日：2016-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chia-Lin Hsu

IPC: H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7853 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795

Abstract: The present invention provides a non-planar FET and a method of manufacturing the same. The non-planar FET includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.

公开(公告)号：US20160020139A1

公开(公告)日：2016-01-21

申请号：US14478609

申请日：2014-09-05

Applicant: United Microelectronics Corp.

Inventor： Wen-Yi Teng ,  Yuh-Min Lin ,  Chih-Chien Liu ,  Chieh-Wen Lo

IPC: H01L21/762 ,  H01L23/58 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67742 ,  H01L21/67766 ,  H01L21/762 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A gap-filling dielectric layer, method for fabricating the same and applications thereof are disclosed. A silicon-containing dielectric layer is firstly deposited on a substrate. The silicon-containing dielectric layer is then subjected to a curing process, an in-situ wetting treatment and an annealing process in sequence, whereby a gap-filling dielectric layer with a nitrogen atom density less than 1×1022 atoms/cm3 is formed.

Abstract translation: 公开了间隙填充介电层，其制造方法及其应用。 首先在基板上沉积含硅介电层。 然后对含硅电介质层进行固化处理，原位润湿处理和退火处理，由此形成氮原子密度小于1×1022原子/ cm3的间隙填充介电层。

公开(公告)号：US20150214114A1

公开(公告)日：2015-07-30

申请号：US14166091

申请日：2014-01-28

Applicant: United Microelectronics Corp.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chun-Hsiung Wang ,  Kun-Ju Li ,  Chia-Lin Hsu ,  Chih-Chien Liu

IPC: H01L21/8234 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/321

CPC classification number: H01L21/823437 ,  H01L21/31051 ,  H01L21/31055 ,  H01L29/66545

Abstract: A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps. A substrate with a plurality of dummy gate structures formed thereon and a first dielectric layer covering the dummy gate structures is provided, the dummy gate structures comprising a plurality of dummy gates and a plurality of insulating layers formed on the dummy gates, wherein at least two of the dummy gate structures have different heights. A first planarization process is performed to expose at least one of the dummy gate structures having the highest height. A first etching process is performed to expose the insulating layers. A chemical mechanical polishing (CMP) process with a non-selectivity slurry is performed to planarize the dummy gate structures. The planarized dummy gate structures are removed to form a plurality of gate trenches.

Abstract translation: 公开了一种半导体结构的制造方法。 该制造方法包括以下步骤。 提供具有形成在其上的多个虚拟栅极结构的基板和覆盖该虚拟栅极结构的第一介电层，所述伪栅极结构包括形成在所述伪栅极上的多个伪栅极和多个绝缘层，其中至少两个 的虚拟门结构具有不同的高度。 执行第一平面化处理以暴露具有最高高度的虚拟栅极结构中的至少一个。 执行第一蚀刻工艺以暴露绝缘层。 进行具有非选择性浆料的化学机械抛光（CMP）工艺以使虚拟栅极结构平坦化。 平面化的虚拟栅极结构被去除以形成多个栅极沟槽。

公开(公告)号：US08927388B2

公开(公告)日：2015-01-06

申请号：US13677318

申请日：2012-11-15

Applicant: United Microelectronics Corp.

Inventor： Jei-Ming Chen ,  Wen-Yi Teng ,  Chia-Lung Chang ,  Chih-Chien Liu

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/3105 ,  H01L21/76229 ,  H01L21/76819 ,  H01L21/76826 ,  H01L21/76837

Abstract: A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma.

Abstract translation: 制造介电层的方法包括以下步骤。 首先，在基板上形成电介质层，对电介质层进行化学机械研磨（CMP）处理。 随后，在化学机械抛光工艺之后对电介质层进行表面处理工艺，并且表面处理工艺包括引入氧等离子体。

公开(公告)号：US08779513B2

公开(公告)日：2014-07-15

申请号：US13869037

申请日：2013-04-24

Applicant: United Microelectronics Corp.

Inventor： Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.

Abstract translation: 非平面半导体结构包括衬底，至少两个鳍状结构，至少一个隔离结构和多个外延层。 鳍状结构位于基底上。 隔离结构位于鳍状结构之间，隔离结构具有含氮层。 外延层分别覆盖了鳍状结构的一部分并且位于含氮层上。 还提供了用于形成半导体结构的非平面半导体工艺。