公开(公告)号：US10283616B2

公开(公告)日：2019-05-07

申请号：US15252200

申请日：2016-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chien Hsieh ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Po-Wen Su

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266 ,  H01L29/78

Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.

公开(公告)号：US20190081150A1

公开(公告)日：2019-03-14

申请号：US16178580

申请日：2018-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Rung-Yuan Lee ,  Chih-Wei Yang

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/49 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606 ,  H01L29/7843

Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.

公开(公告)号：US20180061963A1

公开(公告)日：2018-03-01

申请号：US15252200

申请日：2016-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chien Hsieh ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Po-Wen Su

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.

公开(公告)号：US20170069540A1

公开(公告)日：2017-03-09

申请号：US15356671

申请日：2016-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/10 ,  H01L27/088 ,  H01L29/08 ,  H01L29/06 ,  H01L21/324

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02667 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides a method for forming a semiconductor structure. Firstly, a substrate is provided, the substrate comprises an insulating layer and at least one first nano channel structure disposed thereon, a first region and a second region being defined on the substrate, next, a hard mask is formed within the first region, afterwards, an etching process is performed, to remove parts of the insulating layer within the second region, an epitaxial process is then performed, to form an epitaxial layer on the first nano channel structure, and an anneal process is performed, to transform the first nano channel structure and the epitaxial layer into a first nanowire structure, wherein the diameter of the first nanowire structure within the first region is different from the diameter of the first nanowire structure within the second region.

Abstract translation: 本发明提供一种形成半导体结构的方法。 首先，提供基板，所述基板包括绝缘层和设置在其上的至少一个第一纳米通道结构，在所述基板上限定第一区域和第二区域，接下来，在所述第一区域内形成硬掩模 执行蚀刻处理，以去除第二区域内的绝缘层的部分，然后进行外延工艺，以在第一纳米通道结构上形成外延层，并进行退火工艺以将第一纳米管 沟道结构和外延层形成第一纳米线结构，其中第一区域内的第一纳米线结构的直径不同于第二区域内的第一纳米线结构的直径。

公开(公告)号：US20170025512A1

公开(公告)日：2017-01-26

申请号：US15283445

申请日：2016-10-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/4232 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545

Abstract: A semiconductor device having metal gate includes a substrate, a metal gate formed on the substrate, a pair of spacers formed on sidewalls of the metal gate, a contact etch stop layer (CESL) covering the spacers, an insulating cap layer formed on the metal gate, the spacers and the CESL, and an ILD layer surrounding the metal gate, the spacers, the CESL and the insulating cap layer. The metal gate, the spacers and the CESL include a first width, and the insulating cap layer includes a second width. The second width is larger than the first width. And a bottom of the insulating cap layer concurrently contacts the metal gate, the spacers, the CESL, and the ILD layer.

Abstract translation: 具有金属栅极的半导体器件包括衬底，形成在衬底上的金属栅极，形成在金属栅极的侧壁上的一对间隔物，覆盖间隔物的接触蚀刻停止层（CESL），形成在金属栅极上的绝缘盖层 栅极，间隔物和CESL，以及围绕金属栅极，间隔物，CESL和绝缘帽层的ILD层。 金属栅极，间隔物和CESL包括第一宽度，绝缘帽层包括第二宽度。 第二宽度大于第一宽度。 并且绝缘盖层的底部同时与金属栅极，间隔物，CESL和ILD层接触。

公开(公告)号：US20160293725A1

公开(公告)日：2016-10-06

申请号：US14704994

申请日：2015-05-06

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/4232 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method for manufacturing a semiconductor device having metal gate includes following steps. A substrate is provided. At least a transistor including a dummy gate is formed on the substrate and the transistor is embedded in an interlayer dielectric (ILD) layer. A first removal process is performed to remove a portion of the dummy gate to form a first recess in the transistor. An etching process is subsequently performed to remove a portion of the ILD layer to widen the first recess and to form a widened first recess. A second removal process is subsequently performed to remove the dummy gate entirely and to form a second recess in the transistor. A metal gate is formed in the second recess and followed by forming an insulating cap layer on the metal gate.

Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括以下步骤。 提供基板。 在衬底上形成至少包括伪栅极的晶体管，并且将晶体管嵌入在层间电介质层（ILD）层中。 执行第一去除处理以去除伪栅极的一部分以在晶体管中形成第一凹部。 随后进行蚀刻处理以去除ILD层的一部分以加宽第一凹部并形成加宽的第一凹部。 随后执行第二去除处理以完全去除伪栅极并在晶体管中形成第二凹槽。 在第二凹部中形成金属栅极，然后在金属栅极上形成绝缘盖层。

公开(公告)号：US20160284641A1

公开(公告)日：2016-09-29

申请号：US14692762

申请日：2015-04-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Chih-Sen Huang ,  Yu-Cheng Tung

IPC: H01L23/522 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/3085 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/00 ,  H01L29/66545 ,  H01L29/66553

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; a first hard mask on the gate structure; and a second hard mask on the gate structure, wherein the first hard mask is adjacent to two sides of the second hard mask and the first hard mask and the first hard mask comprises silicon nitride.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：其上具有栅极结构的衬底和围绕栅极结构的第一层间电介质（ILD）层; 栅极结构上的第一个硬掩模; 以及栅极结构上的第二硬掩模，其中所述第一硬掩模与所述第二硬掩模的两侧相邻，并且所述第一硬掩模和所述第一硬掩模包括氮化硅。

公开(公告)号：US09385236B1

公开(公告)日：2016-07-05

申请号：US14748240

申请日：2015-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ying Sun ,  En-Chiuan Liou ,  Ming-Shing Chen ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  G06F17/50

CPC classification number: H01L29/7853 ,  G06F17/5081 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/7856

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a plurality of fin shaped structures and a dummy gate structure. The fin shaped structures are disposed in a substrate, where at least one of the fin shaped structures has a tipped end. The dummy gate structure is disposed on the substrate, and includes an extending portion covering the tipped end.

Abstract translation: 半导体器件及其形成方法，半导体器件包括多个鳍状结构和虚拟栅极结构。 翅片状结构设置在基板中，其中至少一个翅片形结构具有尖端。 虚拟栅极结构设置在基板上，并且包括覆盖端部的延伸部分。

公开(公告)号：US20160190019A1

公开(公告)日：2016-06-30

申请号：US15060572

申请日：2016-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  Yu-Ru Yang ,  En-Chiuan Liou

IPC: H01L21/8238 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Abstract translation: 本发明提供一种形成包括衬底，第一晶体管，第二晶体管和第三晶体管的集成电路的方法。 第一晶体管具有包括第一底部阻挡层，第一功函数金属层和第一金属层的第一金属栅极。 第二晶体管具有包括第二底部阻挡层，第二功函数金属层和第二金属层的第二金属栅极。 第三晶体管具有包括第三底部阻挡层，第三功函数金属层和第三金属层的第三金属栅极。 第一晶体管，第二晶体管和第三晶体管具有相同的导电类型。 第一底部阻挡层的氮浓度>第二底部阻挡层的氮浓度>第三底部阻挡层的氮浓度。

公开(公告)号：US09318389B1

公开(公告)日：2016-04-19

申请号：US14520342

申请日：2014-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  Yu-Ru Yang ,  En-Chiuan Liou

IPC: H01L21/82 ,  H01L27/08 ,  H01L29/49 ,  H01L29/40 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Abstract translation: 本发明提供一种集成电路，其包括衬底，第一晶体管，第二晶体管和第三晶体管。 第一晶体管具有包括第一底部阻挡层，第一功函数金属层和第一金属层的第一金属栅极。 第二晶体管具有包括第二底部阻挡层，第二功函数金属层和第二金属层的第二金属栅极。 第三晶体管具有包括第三底部阻挡层，第三功函数金属层和第三金属层的第三金属栅极。 第一晶体管，第二晶体管和第三晶体管具有相同的导电类型。 第一底部阻挡层的氮浓度>第二底部阻挡层的氮浓度>第三底部阻挡层的氮浓度。