公开(公告)号：US20230027508A1

公开(公告)日：2023-01-26

申请号：US17396493

申请日：2021-08-06

Applicant: United Microelectronics Corp.

Inventor： Kai Jiun Chang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H01L45/00

Abstract: Provided are a resistive random access memory (RRAM) and a manufacturing method thereof. The resistive random access memory includes multiple unit structures disposed on a substrate. Each of the unit structures includes a first electrode, a first metal oxide layer, and a spacer. The first electrode is disposed on the substrate. The first metal oxide layer is disposed on the first electrode. The spacer is disposed on sidewalls of the first electrode and the first metal oxide layer. In addition, the resistive random access memory includes a second metal oxide layer and a second electrode. The second metal oxide layer is disposed on the unit structures and is connected to the unit structures. The second electrode is disposed on the second metal oxide layer.

公开(公告)号：US11437436B2

公开(公告)日：2022-09-06

申请号：US17084609

申请日：2020-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are formed in the first dielectric layer and respectively on the memory region and the logic region of the substrate. A memory cell is disposed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer is formed on the first dielectric layer and continuously covers a top surface and a sidewall of the memory cell and a top surface of the second conductive structure. A second dielectric layer is formed on the first cap. A third conductive structure is formed in the second dielectric layer and penetrates through the first cap layer to contacts the memory cell.

公开(公告)号：US20220271222A1

公开(公告)日：2022-08-25

申请号：US17211875

申请日：2021-03-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Hung Yu ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H01L45/00

Abstract: A resistive random-access memory (RRAM) device includes a bottom electrode, a high work function layer, a resistive material layer, a top electrode and high work function spacers. The bottom electrode, the high work function layer, the resistive material layer and the top electrode are sequentially stacked on a substrate, wherein the resistive material layer includes a bottom part and a top part. The high work function spacers cover sidewalls of the bottom part, thereby constituting a RRAM cell. The present invention also provides a method of forming a RRAM device.

公开(公告)号：US20220130903A1

公开(公告)日：2022-04-28

申请号：US17571519

申请日：2022-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H01L27/24 ,  H01L45/00

Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.

公开(公告)号：US20210028025A1

公开(公告)日：2021-01-28

申请号：US17067409

申请日：2020-10-09

Applicant: United Microelectronics Corp.

Inventor： Chia-Hung Chen ,  Yu-Huang Yeh ,  Chuan-Fu Wang ,  Chin-Chin Tsai

IPC: H01L21/321 ,  H01L21/3213 ,  H01L29/423 ,  H01L27/11568

Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.

公开(公告)号：US10707225B2

公开(公告)日：2020-07-07

申请号：US16792847

申请日：2020-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H01L27/115 ,  H01L27/11568 ,  H01L29/792 ,  H01L21/28

Abstract: A method for fabricating a semiconductor memory device is disclosed. A substrate having a main surface is provided. A memory gate is formed on the main surface of the substrate. The memory has a first sidewall and a second sidewall opposite to the first sidewall. A control gate is formed in proximity to the memory gate. The control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall. A gap is formed between the second sidewall of the memory gate and the third sidewall of the control gate. A first single spacer structure is formed on the first sidewall of the memory gate and a second single spacer structure on the fourth sidewall of the control gate. A gap-filling layer is formed to fill up the gap.

公开(公告)号：US20250008745A1

公开(公告)日：2025-01-02

申请号：US18221872

申请日：2023-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Jiun Chang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20 ,  H10N79/00

Abstract: An RRAM structure includes a bottom electrode, a resistive switching layer, a top electrode, a spacer and a conductive line. The bottom electrode is a first cylinder. The resistive switching layer includes a second cylinder and a three-dimensional disk. A first bottom of the second cylinder directly contacts a top surface of the three-dimensional disk. The top electrode is a third cylinder. The third cylinder includes a top base, a second bottom base and a sidewall. The first cylinder is embedded within the second cylinder and the three-dimensional disk. The second cylinder is embedded within the third cylinder and the second bottom base of the third cylinder directly contacts the top surface of the three-dimensional disk. The spacer surrounds and directly contacts a side surface of the three-dimensional disk. The conductive line encapsulates the top base and the sidewall of the third cylinder.

公开(公告)号：US20240188306A1

公开(公告)日：2024-06-06

申请号：US18096532

申请日：2023-01-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang ,  Hsiang-Hung Peng

IPC: H10B63/00

CPC classification number: H10B63/82

Abstract: A resistive memory device includes a dielectric layer, a first via connection structure, a first stacked structure, and a first insulating structure. The first via connection structure is disposed in the dielectric layer. The first stacked structure is disposed on the first via connection structure and the dielectric layer. The first insulating structure penetrates through a portion of the first stacked structure in a vertical direction and divides the first stacked structure into a first cell unit and a second cell unit. The first cell unit and the second cell unit include a first shared bottom electrode, and the first insulating structure is disposed directly on the first shared bottom electrode.

公开(公告)号：US11871685B2

公开(公告)日：2024-01-09

申请号：US17378795

申请日：2021-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/841 ,  H10N70/011 ,  H10N70/24 ,  H10N70/826 ,  H10N70/8833

Abstract: A RRAM device includes a bottom electrode, a resistive material layer, a high work function layer, a top electrode, a hard mask and high work function sidewall parts. The bottom electrode, the resistive material layer, the high work function layer, the top electrode and the hard mask are sequentially stacked on a substrate. The high work function sidewall parts cover sidewalls of the top electrode and sidewalls of the hard mask, thereby constituting a RRAM cell. A method of forming said RRAM device is also provided.

公开(公告)号：US20230354724A1

公开(公告)日：2023-11-02

申请号：US17750425

申请日：2022-05-23

Applicant: United Microelectronics Corp.

Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H01L45/00 ,  H01L49/02

CPC classification number: H01L45/1253 ,  H01L45/146 ,  H01L28/24 ,  H01L45/1625 ,  H01L45/1616

Abstract: Provided is a resistive memory structure and a manufacturing method thereof. The resistive memory structure includes a substrate, a dielectric layer, a resistive memory device, a hard mask layer, and a spacer. The dielectric layer is located on the substrate. The dielectric layer has an opening. The resistive memory device is located in the opening and has a protrusion outside the opening. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The hard mask layer covers a top surface of the variable resistance layer. The spacer covers a sidewall of the variable resistance layer in the protrusion.