公开(公告)号：US20170036905A1

公开(公告)日：2017-02-09

申请号：US15295997

申请日：2016-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Che Chen ,  Te-Yuan Wu ,  Chia-Huei Lin ,  Hui-Min Wu ,  Kun-Che Hsieh ,  Kuan-Yu Wang ,  Chung-Yi Chiu

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0075 ,  B81B2207/07 ,  B81C1/00246 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0735

Abstract: A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.

Abstract translation: MEMS结构包括衬底，在衬底的前侧上的介电层，介电层之间的MEMS组件，以及设置在介质间介质层内并通过衬底的室。 该腔室在衬底的背面具有开口。 蚀刻停止层设置在介电层内。 该室具有与开口相对的天花板和连接天花板的侧壁。 侧壁包括蚀刻停止层的一部分。

公开(公告)号：US09306045B2

公开(公告)日：2016-04-05

申请号：US14083551

申请日：2013-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Chung-Yi Chiu

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/08

CPC classification number: H01L29/7395 ,  H01L29/0834

Abstract: A semiconductor power device is provided, comprising a substrate of a first conductive type, a buffering layer of a second conductive type formed on the substrate, a voltage supporting layer formed on the buffering layer, and alternating sections of different conductive types formed at the substrate. The voltage supporting layer comprises first semiconductor regions of the first conductive type and second semiconductor regions of the second conductive type, wherein the first semiconductor regions and the second semiconductor regions are alternately arranged. The alternating section and the buffering layer form a segmented structure of alternated conductive types, which is used as an anode of the semiconductor device.

Abstract translation: 提供了一种半导体功率器件，包括第一导电类型的衬底，形成在衬底上的第二导电类型的缓冲层，形成在缓冲层上的电压支撑层，以及形成在衬底上的不同导电类型的交替部分 。 电压支撑层包括第一导电类型的第一半导体区域和第二导电类型的第二半导体区域，其中第一半导体区域和第二半导体区域交替布置。 交替部分和缓冲层形成交替导电类型的分段结构，其用作半导体器件的阳极。

公开(公告)号：US20150064869A1

公开(公告)日：2015-03-05

申请号：US14018439

申请日：2013-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Hong ,  Chung-Yi Chiu

IPC: H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/845 ,  H01L29/6681

Abstract: The present invention provides a method of forming Fin-FET. A substrate with an active region and a dummy region are defined thereon. A plurality of first fins and second fins are formed in the active region, and a plurality of dummy fins are formed in the dummy region and the active region. A first active region is provided in the active region. A revised first active region is formed by extending the first active region to cover at least one adjacent dummy fin. Next, a first dummy region is provided in the dummy region. A first mask layout is formed by combining the revised first active region and the first dummy region. A first patterned mask layer is formed by using the first mask layout. A first epitaxial process is performed for the first fins and the dummy fins exposed by the first patterned mask layer.

Abstract translation: 本发明提供一种形成Fin-FET的方法。 在其上限定具有有源区和虚拟区的衬底。 多个第一鳍片和第二鳍片形成在有源区域中，并且在虚拟区域和有源区域中形成多个虚设翅片。 在活动区域​​中设置第一有源区域。 经修改的第一有源区通过延伸第一有源区以覆盖至少一个相邻的虚拟鳍形成。 接下来，在虚拟区域中设置第一虚拟区域。 通过组合经修改的第一有源区和第一伪区形成第一掩模布局。 通过使用第一掩模布局形成第一图案化掩模层。 对由第一图案化掩模层暴露的第一鳍片和虚拟鳍片执行第一外延工艺。

公开(公告)号：US12293941B2

公开(公告)日：2025-05-06

申请号：US17835983

申请日：2022-06-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H10D64/00 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

Abstract: A gallium nitride (GaN) device with field plate structure, including a substrate, a gate on the substrate and a passivation layer covering on the gate, a source and a drain on the substrate and the passivation layer, a stop layer on the source, the drain and the passivation layer, and dual-damascene interconnects connecting respectively with the source and the drain, wherein the dual-damascene interconnect is provided with a via portion under the stop layer and a trench portion on the stop layer, and the via portion is connected with the source or the drain, and the trench portion of one of the dual-damascene interconnects extends horizontally toward the drain and overlaps the gate below in vertical direction, thereby functioning as a field plate structure for the GaN device.

公开(公告)号：US20240422989A1

公开(公告)日：2024-12-19

申请号：US18223043

申请日：2023-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

Abstract: A resistive memory device includes a dielectric layer, a trench, a first resistive switching element, a diode via structure, and a signal line structure. The trench is disposed in the dielectric layer. The first resistive switching element is disposed in the trench. The first resistive switching element includes a first bottom electrode, a first top electrode disposed above the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode. The diode via structure is disposed in the dielectric layer and located under the trench, and the diode via structure is connected with the first bottom electrode. The signal line structure is disposed in the trench, a part of the signal line structure is disposed on the first resistive switching element, and the signal line structure is electrically connected with the first top electrode.

公开(公告)号：US20240162208A1

公开(公告)日：2024-05-16

申请号：US18077192

申请日：2022-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Chih-Wei Chang ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L25/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66 ,  H01L29/778 ,  H01L31/0224 ,  H01L31/0304 ,  H01L31/0352 ,  H01L31/18 ,  H03H3/08 ,  H03H9/02

CPC classification number: H01L25/167 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/454 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7786 ,  H01L31/022408 ,  H01L31/03044 ,  H01L31/035236 ,  H01L31/1856 ,  H03H3/08 ,  H03H9/02976

Abstract: A structure with a photodiode, an HEMT and an SAW device includes a photodiode and an HEMT. The photodiode includes a first electrode and a second electrode. The first electrode contacts a P-type III-V semiconductor layer. The second electrode contacts an N-type III-V semiconductor layer. The HEMT includes a P-type gate disposed on an active layer. A gate electrode is disposed on the P-type gate. Two source/drain electrodes are respectively disposed at two sides of the P-type gate. Schottky contact is between the first electrode and the P-type III-V semiconductor layer, and between the gate electrode and the P-type gate. Ohmic contact is between the second electrode and the first N-type III-V semiconductor layer, and between one of the two source/drain electrodes and the active layer and between the other one of two source/drain electrodes and the active layer.

公开(公告)号：US20240016063A1

公开(公告)日：2024-01-11

申请号：US17884528

申请日：2022-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu ,  Shun-Yu Huang ,  Yi-Wei Tseng

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

Abstract: An MRAM structure includes an MTJ, a first SOT element, a conductive layer and a second SOT element disposed from bottom to top. A protective layer is disposed on the second SOT element. The protective layer covers and contacts a top surface of the second SOT element. The protective layer is an insulator. A conductive via penetrates the protective layer and contacts the second SOT element.

公开(公告)号：US20230413695A1

公开(公告)日：2023-12-21

申请号：US18239108

申请日：2023-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/826 ,  H10N70/231 ,  H10N70/011 ,  H10B63/00

Abstract: A manufacturing method of a memory device includes following steps. A memory unit including a first electrode, a second electrode, and a memory material layer is formed on a substrate. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A first spacer layer including a first portion, a second portion, and a third portion is formed on a sidewall of the memory unit. The first portion is disposed on a sidewall of the first electrode. The second portion is disposed on a sidewall of the second electrode. The third portion is disposed above the memory unit in the vertical direction and connected with the second portion. A thickness of the second portion in a horizontal direction is greater than that of the first portion in the horizontal direction.

公开(公告)号：US20230378275A1

公开(公告)日：2023-11-23

申请号：US17844746

申请日：2022-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L29/66462 ,  H01L29/205 ,  H01L29/7786

Abstract: A semiconductor device includes a III-V compound semiconductor layer, a silicon-doped III-V compound barrier layer, and a silicon-rich tensile stress layer. The silicon-doped III-V compound barrier layer is disposed on the III-V compound semiconductor layer, and the silicon-rich tensile stress layer is disposed on the silicon-doped III-V compound barrier layer. A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A silicon-rich tensile stress layer is formed on the III-V compound barrier layer. An annealing process is performed after the silicon-rich tensile stress layer is formed. A part of silicon in the silicon-rich tensile stress layer diffuses into the III-V compound barrier layer for forming a silicon-doped III-V compound barrier layer by the annealing process.

公开(公告)号：US20230350381A1

公开(公告)日：2023-11-02

申请号：US17749176

申请日：2022-05-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Ting Pan ,  Chung-Yi Chiu

IPC: G05B19/4099 ,  G06T7/13 ,  G06T7/73 ,  G03F7/20

CPC classification number: G05B19/4099 ,  G06T7/13 ,  G06T7/73 ,  G03F7/705 ,  G06T2207/10061 ,  G06T2207/30148 ,  G05B2219/35134

Abstract: A method of simulating a 3D feature profile by using a scanning electron microscope (SEM) image includes providing an SEM image. The SEM image includes a feature pattern within a material layer. The feature pattern includes an inner edge and an outer edge. The outer edge surrounds the inner edge. Then, the positions of the inner edge and the outer edge of the feature pattern are identified. Latter, a side edge region is defined based on the positions of the inner edge and the outer edge. Subsequently, a side edge model is generated automatically to simulate a profile of the feature pattern in the side edge region. Finally, a 3D feature profile is automatically output based on the position of the inner edge, the position of the outer edge, the thickness of the material layer and the side edge profile.