公开(公告)号：US10446448B2

公开(公告)日：2019-10-15

申请号：US16175776

申请日：2018-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Chun-Tsen Lu ,  Shou-Wei Hsieh

IPC: H01L29/06 ,  H01L21/8234

Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; a first oxide layer on the first fin-shaped structure; a second oxide layer on and directly contacting the first oxide layer and the STI; and a third oxide layer on the second fin-shaped structure, wherein a thickness of the third oxide layer is less than a thickness of the first oxide layer.

公开(公告)号：US10431652B2

公开(公告)日：2019-10-01

申请号：US15834082

申请日：2017-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L29/10 ,  H01L29/775 ,  B82Y10/00 ,  H01L21/324

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.

公开(公告)号：US10340272B2

公开(公告)日：2019-07-02

申请号：US15947862

申请日：2018-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Shou-Wei Hsieh ,  Hsin-Yu Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/51 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088

Abstract: A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. The barrier layer formed in the first region is thinned before a step of forming a first work function layer on the barrier layer. The first work function layer formed on the first region is then removed. The process of thinning the barrier layer in the first region and the process of removing the first work function layer in the first region are performed separately for ensuring the coverage of the first work function layer in the second region. The electrical performance of the semiconductor device and the uniformity of the electrical performance of the semiconductor device may be improved accordingly.

公开(公告)号：US20190189525A1

公开(公告)日：2019-06-20

申请号：US16280043

申请日：2019-02-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/161 ,  H01L27/092

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first gate structure on the first region and a second gate structure on the second region; forming a first spacer around the first gate structure; forming a first epitaxial layer adjacent to two sides of the first spacer; forming a buffer layer on the first gate structure; and forming a contact etch stop layer (CESL) on the buffer layer on the first region and the second gate structure on the second region.

公开(公告)号：US20190131453A1

公开(公告)日：2019-05-02

申请号：US15821860

申请日：2017-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Chun-Jung Tang ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/762

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/167 ,  H01L29/42356 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7848 ,  H01L29/7851

Abstract: A tunnel field effect transistor (TFET) includes: a first gate structure on a substrate; a source region having a first conductive type on one side of the first gate structure; a drain region having a second conductive type on another side of the first gate structure; a first isolation structure adjacent to the source region; and a second isolation structure adjacent to the drain region. Preferably, the first isolation and the second isolation comprise different material and different depths or same material and different depths.

公开(公告)号：US10256160B1

公开(公告)日：2019-04-09

申请号：US15786608

申请日：2017-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L21/8238 ,  H01L29/161 ,  H01L27/092 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first gate structure on the first region and a second gate structure on the second region; forming a first spacer around the first gate structure; forming a first epitaxial layer adjacent to two sides of the first spacer; forming a buffer layer on the first gate structure; and forming a contact etch stop layer (CESL) on the buffer layer on the first region and the second gate structure on the second region.

公开(公告)号：US20190067118A1

公开(公告)日：2019-02-28

申请号：US16175776

申请日：2018-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Chun-Tsen Lu ,  Shou-Wei Hsieh

IPC: H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/823462 ,  H01L21/823431

Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; a first oxide layer on the first fin-shaped structure; a second oxide layer on and directly contacting the first oxide layer and the STI; and a third oxide layer on the second fin-shaped structure, wherein a thickness of the third oxide layer is less than a thickness of the first oxide layer.

公开(公告)号：US20180350938A1

公开(公告)日：2018-12-06

申请号：US15984426

申请日：2018-05-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Ming Lee ,  Sheng-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/4991 ,  H01L21/28088 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785

Abstract: A method for fabricating semiconductor device includes the steps of first forming a metal gate on a substrate and a spacer around the metal gate, in which the metal gate comprises a high-k dielectric layer, a work function metal layer, and a low-resistance metal layer. Next, part of the high-k dielectric layer is removed to form an air gap between the work function metal layer and the spacer.

公开(公告)号：US10008578B1

公开(公告)日：2018-06-26

申请号：US15642324

申请日：2017-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Ming Lee ,  Sheng-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L21/70 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/4991 ,  H01L21/28026 ,  H01L21/28088 ,  H01L21/28114 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785

Abstract: A method for fabricating semiconductor device includes the steps of first forming a metal gate on a substrate and a spacer around the metal gate, in which the metal gate comprises a high-k dielectric layer, a work function metal layer, and a low-resistance metal layer. Next, part of the high-k dielectric layer is removed to form an air gap between the work function metal layer and the spacer.

公开(公告)号：US20170222026A1

公开(公告)日：2017-08-03

申请号：US15014037

申请日：2016-02-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ren Chen ,  Shou-Wei Hsieh ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Yuan-Ting Chuang ,  Che-Hung Liu

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L29/66795 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/31111 ,  H01L29/66545 ,  H01L29/7847

Abstract: The present invention provides a method of fabricating a fin field effect transistor (finFET), comprising: firstly, an interfacial layer is formed on a fin structure, next, a high-k dielectric layer is formed on the interfacial layer; afterwards, a stress film is formed on the high-k dielectric layer, an annealing process is then performed to the stress film, and an etching process is performed to remove the stress film.