公开(公告)号：US08853060B1

公开(公告)日：2014-10-07

申请号：US13902862

申请日：2013-05-27

Applicant: United Microelectronics Corp.

Inventor： Szu-Hao Lai ,  Chun-Yuan Wu ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Tsai-Yu Wen ,  Hsin-Kuo Hsu

IPC: H01L21/20 ,  H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: An epitaxial process includes the following step. A recess is formed in a substrate. A seeding layer is formed to cover a surface of the recess. A buffer layer is formed on the seeding layer. An etching process is performed on the buffer layer to homogenize and shape the buffer layer. An epitaxial layer is formed on the homogenized flat bottom shape buffer layer.

Abstract translation: 外延工艺包括以下步骤。 在基板上形成凹部。 形成接合层以覆盖凹部的表面。 在接种层上形成缓冲层。 对缓冲层进行蚀刻处理，使缓冲层均匀化并形成。 在均质化的平底形状缓冲层上形成外延层。

公开(公告)号：US12237415B2

公开(公告)日：2025-02-25

申请号：US18234889

申请日：2023-08-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Tang ,  Chung-Ting Huang ,  Bo-Shiun Chen ,  Chun-Jen Chen ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.

公开(公告)号：US20240304705A1

公开(公告)日：2024-09-12

申请号：US18665600

申请日：2024-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/6656 ,  H01L29/42364

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

公开(公告)号：US20240266437A1

公开(公告)日：2024-08-08

申请号：US18635018

申请日：2024-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yu Chen ,  Bo-Lin Huang ,  Jhong-Yi Huang ,  Keng-Jen Lin ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L29/16

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.

公开(公告)号：US20210287944A1

公开(公告)日：2021-09-16

申请号：US17337446

申请日：2021-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin

IPC: H01L21/8234 ,  H01L21/324 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of providing a substrate having a first region and a second region, forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, and forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature and a center of curvature of the first fin-shaped structure is lower than a top surface of the STI and a center of curvature of the second fin-shaped structure is higher than the top surface of the STI.

公开(公告)号：US10510609B2

公开(公告)日：2019-12-17

申请号：US15885834

申请日：2018-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/324 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; forming a mask layer on the first fin-shaped structure; and performing a first anneal process so that the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature.

公开(公告)号：US09966434B2

公开(公告)日：2018-05-08

申请号：US15632399

申请日：2017-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Yi-Wei Chen ,  I-Cheng Hu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/165 ,  H01L29/36 ,  H01L21/265 ,  H01L21/324 ,  H01L29/167 ,  H01L21/283 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/324 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53252 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

公开(公告)号：US20170373191A1

公开(公告)日：2017-12-28

申请号：US15214429

申请日：2016-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Chen Chan ,  Yi-Fan Li ,  Li-Wei Feng ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Shu-Yen Chan

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02164 ,  H01L21/0217 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. First, a fin-shaped structure is formed on a substrate, a first liner is formed on the substrate and the fin-shaped structure, a second liner is formed on the first liner, part of the second liner and part of the first liner are removed to expose a top surface of the fin-shaped structure, part of the first liner between the fin-shaped structure and the second liner is removed to form a recess, and an epitaxial layer is formed in the recess.

公开(公告)号：US09754938B1

公开(公告)日：2017-09-05

申请号：US15187800

申请日：2016-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Tong-Jyun Huang ,  Shih-Hung Tsai ,  Jia-Rong Wu ,  Tien-Chen Chan ,  Yu-Shu Lin ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped structures. The epitaxial layers respectively conformally and directly cover the fin-shaped structures in the first region. The gate electrode covers the fin-shaped structures in the second region, and the protection layer is disposed between the gate electrode and the fin-shaped structures.

公开(公告)号：US09748147B1

公开(公告)日：2017-08-29

申请号：US15214467

申请日：2016-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Li-Wei Feng ,  Li-Chieh Hsu ,  Chun-Jen Chen ,  I-Cheng Hu ,  Tien-I Wu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L21/20 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02661 ,  H01L21/2652 ,  H01L21/3086 ,  H01L21/823807 ,  H01L21/8258

Abstract: A method of fabricating an epitaxial layer includes providing a silicon substrate. A dielectric layer covers the silicon substrate. A recess is formed in the silicon substrate and the dielectric layer. A selective epitaxial growth process and a non-selective epitaxial growth process are performed in sequence to respectively form a first epitaxial layer and a second epitaxial layer. The first epitaxial layer does not cover the top surface of the dielectric layer. The recess is filled by the first epitaxial layer and the second epitaxial layer. Finally, the first epitaxial layer and the second epitaxial layer are planarized.