公开(公告)号：US20220068872A1

公开(公告)日：2022-03-03

申请号：US17030380

申请日：2020-09-24

Applicant: Unimicron Technology Corp.

Inventor： Chia-Fu Hsu ,  Kai-Ming Yang ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L23/00

Abstract: A fabrication method of an electronic device bonding structure includes the following steps. A first electronic component including a first conductive bonding portion is provided. A second electronic component including a second conductive bonding portion is provided. A first organic polymer layer is formed on the first conductive bonding portion. A second organic polymer layer is formed on the second conductive bonding portion. Bonding is performed on the first electronic component and the second electronic component through the first conductive bonding portion and the second conductive bonding portion, such that the first electronic component and the second electronic component are electrically connected. The first organic polymer layer and the second organic polymer layer diffuse into the first conductive bonding portion and the second conductive bonding portion after the bonding. An electronic device bonding structure is also provided.

公开(公告)号：US11166387B2

公开(公告)日：2021-11-02

申请号：US16847688

申请日：2020-04-14

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Pu-Ju Lin

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H05K3/22

Abstract: A wiring board including a build-up circuit layer, a patterned conductive layer, first and second adhesion promoting material layers and first and second solder mask layers is provided. The build-up circuit layer has a first surface and a second surface opposite thereto. The patterned conductive layer is disposed on the second surface. The first adhesion promoting material layer is disposed on the first surface and includes at least one first opening. The second adhesion promoting material layer is disposed on the second surface and the patterned conductive layer, and includes at least one second opening. The first solder mask layer is disposed on the first adhesion promoting material layer and includes at least one third opening provided corresponding to the first opening. The second solder mask layer is disposed on the second adhesion promoting material layer and includes at least one fourth opening provided corresponding to the second opening.

公开(公告)号：US20210296291A1

公开(公告)日：2021-09-23

申请号：US16846429

申请日：2020-04-13

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L25/075 ,  H01L33/62 ,  H01L33/52 ,  H01L33/00

Abstract: A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit layer have been formed on the carrier. A flat structure layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and covers the flat structure layer and a portion of the first dielectric layer. A second patterned circuit layer is formed on the second dielectric layer. The second patterned circuit layer includes a plurality of pads. An orthographic projection of the flat structure layer on the carrier overlaps orthographic projections of the pads on the carrier. A plurality of chips are disposed on the pads. A molding compound is formed to cover the second dielectric layer and encapsulate the chips and the pads.

公开(公告)号：US20210118839A1

公开(公告)日：2021-04-22

申请号：US16687557

申请日：2019-11-18

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Cheng-Ta Ko ,  Ra-Min Tain ,  Tzyy-Jang Tseng

IPC: H01L23/00 ,  H01L23/538

Abstract: A chip package structure includes a substrate, at least two chips, a plurality of first pads, a plurality of first micro bumps, and a bridging element. The substrate has a first surface and a second surface opposite to the first surface. The two chips are disposed on the first surface of the substrate and are horizontally adjacent to each other. Each chip has an active surface. The first pads are disposed on the active surface of each of the chips. The first micro bumps are disposed on the first pads and have the same size. The bridging element is disposed on the first micro bumps such that one of the chips is electrically connected to another of the chips through the first pads, the first micro bumps, and the bridging element.

公开(公告)号：US10957658B2

公开(公告)日：2021-03-23

申请号：US16866530

申请日：2020-05-04

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Cheng-Ta Ko ,  Yu-Hua Chen ,  Tzyy-Jang Tseng ,  Ra-Min Tain

IPC: H01L23/16 ,  H01L23/66 ,  H01L23/00 ,  H01L23/31

Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.

公开(公告)号：US10950535B2

公开(公告)日：2021-03-16

申请号：US16785630

申请日：2020-02-09

Applicant: Unimicron Technology Corp.

Inventor： Chun-Min Wang ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00

Abstract: A package structure includes a redistribution structure, a chip, an inner conductive reinforcing element, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The inner conductive reinforcing element is disposed over the redistribution structure. The inner conductive reinforcing element has a Young's modulus in a range of from 30 to 200 GPa. The protective layer covers the chip and a sidewall of an opening of the inner conductive reinforcing element.

公开(公告)号：US12062742B2

公开(公告)日：2024-08-13

申请号：US17653659

申请日：2022-03-07

Applicant: Unimicron Technology Corp.

Inventor： Hao-Wei Tseng ,  Chi-Hai Kuo ,  Jeng-Ting Li ,  Ying-Chu Chen ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L33/54 ,  H01L23/00 ,  H01L25/075

CPC classification number: H01L33/54 ,  H01L24/83 ,  H01L25/0753 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/29194 ,  H01L2224/32227 ,  H01L2224/83099 ,  H01L2224/83203 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/8389 ,  H01L2924/12041 ,  H01L2933/005

Abstract: A package structure includes a substrate, a plurality of conductive pads, a light-emitting diode, a photo imageable dielectric material, and a black matrix. The substrate includes a top surface. The conductive pads are located on the top surface of the substrate. The light-emitting diode is located on the conductive pads. The photo imageable dielectric material is located between the light-emitting diode and the top surface of the substrate and between the conductive pads. An orthogonal projection of the light-emitting diode on the substrate is overlapped with an orthogonal projection of the photo imageable dielectric material on the substrate. The black matrix is located on the top surface of the substrate and the conductive pads.

公开(公告)号：US20240251504A1

公开(公告)日：2024-07-25

申请号：US18172324

申请日：2023-02-22

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Chin-Sheng Wang ,  Cheng-Ta Ko ,  Pu-Ju Lin

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H05K3/067 ,  H05K3/4679 ,  H05K2201/09454 ,  H05K2203/0789

Abstract: The invention provides a circuit board structure and a manufacturing method thereof. The circuit board structure includes a line portion, a first insulating layer, and a conductive terminal. The first insulating layer is disposed on the line portion. The conductive terminal is disposed on the first insulating layer and embedded in the first insulating layer to be electrically connected with the line portion. The conductive terminal includes a first portion, a second portion, and a third portion. The first portion protrudes from a surface of the first insulating layer. The second portion is embedded in the first insulating layer and connected to the first portion. The third portion is disposed between the line portion and the second portion. A width of the second portion is greater than a width of the third portion.

公开(公告)号：US11764344B2

公开(公告)日：2023-09-19

申请号：US17209110

申请日：2021-03-22

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang

IPC: H01L33/62 ,  H01L33/06 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L33/54

CPC classification number: H01L33/06 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L33/54 ,  H01L2221/6835 ,  H01L2933/005 ,  H01L2933/0066

Abstract: A manufacturing method of a package structure is provided, which includes the following steps. A carrier having a surface is provided. A copper foil layer is laminated on the surface of the carrier. A subtractive process is performed on the copper foil layer to form a copper foil circuit layer on the carrier. The copper foil circuit layer exposes a part of the surface of the carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the carrier. A first surface of the copper foil circuit layer is aligned with a second surface of the build-up structure layer. At least one electronic component is disposed on the build-up structure layer. A package colloid is formed to cover the electronic component and the build-up structure layer. The carrier is removed to expose the first surface of the copper foil circuit layer.

公开(公告)号：US20230240023A1

公开(公告)日：2023-07-27

申请号：US17684421

申请日：2022-03-02

Applicant: Unimicron Technology Corp.

Inventor： Wen-Yu Lin ,  Kai-Ming Yang ,  Chen-Hao Lin ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Chin-Sheng Wang ,  Guang-Hwa Ma ,  Tzyy-Jang Tseng

IPC: H05K3/46 ,  H05K1/11

CPC classification number: H05K3/467 ,  H05K1/112 ,  H05K2201/0191

Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.