公开(公告)号：US11387408B2

公开(公告)日：2022-07-12

申请号：US17131767

申请日：2020-12-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  Jing-Yin Jhang ,  I-Ming Tseng ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Kun-Chen Ho ,  Yi-Syun Chou ,  Chang-Min Li ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  Jun Xie

IPC: H01L29/82 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

公开(公告)号：US10727397B1

公开(公告)日：2020-07-28

申请号：US16261524

申请日：2019-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yi-Wei Tseng ,  Meng-Jun Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  I-Ming Tseng

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L45/00 ,  H01L27/108 ,  H01L43/10

Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.

公开(公告)号：US20180288326A1

公开(公告)日：2018-10-04

申请号：US16001367

申请日：2018-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin

IPC: H04N5/232 ,  G02B26/10 ,  H04N5/225 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L21/764 ,  H01L21/3213 ,  H01L21/283 ,  H01L21/02

CPC classification number: H04N5/23238 ,  G02B26/101 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/283 ,  H01L21/32135 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H04N5/2254 ,  H04N5/2259 ,  H04N5/23254 ,  H04N5/23258 ,  H04N5/23287

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a gate structure, a first dielectric layer and two air gaps. The gate structure is disposed on the substrate. The gate structure has two opposite side walls. The gate structure comprises a U-shaped structure and a metal gate electrode. The U-shaped structure defines an opening toward upside, and comprises a work function layer. The metal gate electrode is disposed in the opening defined by the U-shaped structure. A level of a top surface of the U-shaped structure is lower than a level of a top surface of the metal gate electrode. The first dielectric layer is disposed on the substrate adjacent to the gate structure. Each of the two air gaps is formed between the first dielectric layer and one of the two opposite side walls of the gate structure.

公开(公告)号：US09847403B2

公开(公告)日：2017-12-19

申请号：US14855357

申请日：2015-09-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L29/6656 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, gate electrodes, spacers and contact structures. The gate electrodes are disposed on the substrate, and the spacers are disposed on the sidewalls of the gate electrodes. Each of the spacers has an inner sidewall and an outer sidewall. The contact structure is disposed between the gate electrodes, and its bottom is in direct contact with all the region of the outer sidewall of the spacers.

公开(公告)号：US20170194423A1

公开(公告)日：2017-07-06

申请号：US15011996

申请日：2016-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/283 ,  H01L21/764 ,  H01L21/3213 ,  H01L29/78 ,  H01L29/66

CPC classification number: H04N5/23238 ,  G02B26/101 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/283 ,  H01L21/32135 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H04N5/2254 ,  H04N5/2259 ,  H04N5/23254 ,  H04N5/23258 ,  H04N5/23287

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a gate structure, a first dielectric layer and two air gaps. The gate structure is disposed on the substrate. The gate structure has two opposite side walls. The gate structure comprises a U-shaped structure and a metal gate electrode. The U-shaped structure defines an opening toward upside, and comprises a work function layer. The metal gate electrode is disposed in the opening defined by the U-shaped structure. A level of a top surface of the U-shaped structure is lower than a level of a top surface of the metal gate electrode. The first dielectric layer is disposed on the substrate adjacent to the gate structure. Each of the two air gaps is formed between the first dielectric layer and one of the two opposite side walls of the gate structure.

公开(公告)号：US20170125579A1

公开(公告)日：2017-05-04

申请号：US15399755

申请日：2017-01-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/283 ,  H01L21/31105 ,  H01L21/32131 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681

Abstract: A semiconductor device includes: a substrate having a first fin-shaped structure and a second fin-shaped structure thereon, a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure, a gate isolation directly on the second fin-shaped structure, and a gate line on the STI and the first fin-shaped structure. Preferably, the gate line includes a L-shaped structure.

公开(公告)号：US09601600B2

公开(公告)日：2017-03-21

申请号：US14855793

申请日：2015-09-16

Applicant: United Microelectronics Corp.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Cho-Han Fan ,  Chien-Ting Lin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

Abstract: A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fin together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer.

公开(公告)号：US09583600B1

公开(公告)日：2017-02-28

申请号：US14877950

申请日：2015-10-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/283 ,  H01L21/311 ,  H01L29/423 ,  H01L21/3213

CPC classification number: H01L29/785 ,  H01L21/283 ,  H01L21/31105 ,  H01L21/32131 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and shallow trench isolation (STI) around the fin-shaped structure; forming a gate line across the fin-shaped structure and on the STI; performing a first cutting process to remove the part of the gate line directly above the fin-shaped structure and the fin-shaped structure directly under the gate line; and performing a second cutting process to remove part of the gate line on the STI.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有鳍状结构的衬底和围绕鳍状结构的浅沟槽隔离（STI）; 在鳍状结构和STI上形成栅极线; 执行第一切割处理以直接在栅极线下方去除鳍状结构正上方的栅极线的一部分和鳍状结构; 并执行第二切割处理以去除STI上的栅极线的一部分。

公开(公告)号：US20170047426A1

公开(公告)日：2017-02-16

申请号：US15335418

申请日：2016-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin ,  Shih-Hung Tsai

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L21/762 ,  H01L29/08

CPC classification number: H01L29/66598 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7851

Abstract: A complementary metal oxide semiconductor field-effect transistor (MOSFET) includes a substrate, a first MOSFET and a second MOSFET. The first MOSFET is disposed on the substrate within a first transistor region and the second MOSFET is disposed on the substrate within a second transistor region. The first MOSFET includes a first fin structure, two first lightly-doped regions, two first doped regions and a first gate structure. The first fin structure includes a first body portion and two first epitaxial portions, wherein each of the first epitaxial portions is disposed on each side of the first body portion. A first vertical interface is between the first body portion and each of the first epitaxial portions so that the first-lightly doped region is able to be uniformly distributed on an entire surface of each first vertical interface.

Abstract translation: 互补金属氧化物半导体场效应晶体管（MOSFET）包括衬底，第一MOSFET和第二MOSFET。 第一MOSFET设置在第一晶体管区域内的衬底上，并且第二MOSFET设置在第二晶体管区域内的衬底上。 第一MOSFET包括第一鳍结构，两个第一轻掺杂区，两个第一掺杂区和第一栅结构。 第一翅片结构包括第一主体部分和两个第一外延部分，其中每个第一外延部分设置在第一主体部分的每一侧上。 第一垂直接口位于第一主体部分和第一外延部分之间，使得第一轻掺杂区域能够均匀分布在每个第一垂直界面的整个表面上。

公开(公告)号：US09553026B1

公开(公告)日：2017-01-24

申请号：US14960447

申请日：2015-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Chien-Ting Lin ,  Li-Chiang Chen ,  Jyh-Shyang Jenq

IPC: H01L21/30 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/088 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/3086 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first mandrel, a second mandrel, a third mandrel, and a fourth mandrel are formed on the substrate. Preferably, the first mandrel and the second mandrel include a first gap therebetween, the second mandrel and the third mandrel include a second gap therebetween, and the third mandrel and the fourth mandrel include a third gap therebetween, in which the first gap is equivalent to the third gap but different from the second gap. Next, spacers are formed adjacent to the first mandrel, the second mandrel, the third mandrel, and the fourth mandrel, and the spacers in the first gap and the third gap are removed.

Abstract translation: 公开了半导体器件的制造方法。 首先，设置基板，在基板上形成第一芯轴，第二心轴，第三心轴，第四心轴。 优选地，第一心轴和第二心轴包括其间的第一间隙，第二心轴和第三心轴在其间包括第二间隙，并且第三心轴和第四心轴在其间包括第三间隙，其中第一间隙等于 第三个差距，但与第二个差距不同。 接下来，在第一心轴，第二心轴，第三心轴和第四心轴附近形成间隔物，并且去除第一间隙和第三间隙中的间隔物。