公开(公告)号：US20180323256A1

公开(公告)日：2018-11-08

申请号：US16040319

申请日：2018-07-19

Applicant: United Microelectronics Corp.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee ,  Yu-Ru Yang ,  Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Cheng-Tzung Tsai

IPC: H01L29/06 ,  H01L29/10 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225

CPC classification number: H01L29/0615 ,  H01L21/2253 ,  H01L21/76802 ,  H01L21/76871 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

公开(公告)号：US20180053826A1

公开(公告)日：2018-02-22

申请号：US15797011

申请日：2017-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L29/165 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US20160351712A1

公开(公告)日：2016-12-01

申请号：US14754708

申请日：2015-06-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hsin-Yu Chen ,  Hao-Ming Lee

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/3105 ,  H01L29/49 ,  H01L21/324 ,  H01L21/28 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an interlayer dielectric (ILD) layer around the gate structure; removing the gate structure to form a recess; forming a stress layer in the recess, wherein the stress layer comprises metal; and forming a work function layer on the stress layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在基板上形成栅极结构; 在所述栅极结构周围形成层间电介质（ILD）层; 移除所述门结构以形成凹部; 在所述凹部中形成应力层，其中所述应力层包括金属; 并在应力层上形成功函数层。

公开(公告)号：US09508834B1

公开(公告)日：2016-11-29

申请号：US14873173

申请日：2015-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Ming Lee ,  Sheng-Hao Lin ,  Huai-Tzu Chiang

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/161 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L29/66818 ,  H01L21/02 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7854

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, wherein the fin-shaped structure comprises a top portion and a bottom portion; removing part of the STI to expose the top portion of the fin-shaped structure; and performing an oxidation process on the exposed top portion of the fin-shaped structure to divide the top portion into a first top portion and a second top portion while forming an oxide layer around the first top portion.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有鳍状结构的衬底和围绕鳍状结构的浅沟槽隔离（STI），其中鳍状结构包括顶部和底部; 去除STI的一部分以暴露鳍状结构的顶部; 以及在所述鳍状结构的所述暴露的顶部上进行氧化处理，以将所述顶部分成第一顶部和第二顶部，同时在所述第一顶部周围形成氧化物层。

公开(公告)号：US09431482B2

公开(公告)日：2016-08-30

申请号：US14614392

申请日：2015-02-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Sheng-Hao Lin ,  Huai-Tzu Chiang ,  Hao-Ming Lee

IPC: H01L29/06 ,  H01L21/32 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L29/10

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/3247 ,  H01L29/0669 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides some methods for forming at least two different nanowire structures with different diameters on one substrate. Since the diameter of the nanowire structure will influence the threshold voltage (Vt) and the drive currents of a nanowire field effect transistor, in this invention, at least two nanowire structures with different diameters can be formed on one substrate. Therefore, in the following steps, these nanowire structures can be applied in different nanowire field effect transistors with different Vt and drive currents. This way, the flexibility of the nanowire field effect transistors can be improved.

Abstract translation: 本发明提供了在一个基底上形成具有不同直径的至少两种不同纳米线结构的一些方法。 由于纳米线结构的直径将影响纳米线场效应晶体管的阈值电压（Vt）和驱动电流，所以在本发明中，可以在一个衬底上形成具有不同直径的至少两个纳米线结构。 因此，在以下步骤中，这些纳米线结构可以应用于具有不同Vt和驱动电流的不同纳米线场效应晶体管中。 这样，可以提高纳米线场效应晶体管的灵活性。

公开(公告)号：US20160225850A1

公开(公告)日：2016-08-04

申请号：US14614392

申请日：2015-02-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Sheng-Hao Lin ,  Huai-Tzu Chiang ,  Hao-Ming Lee

IPC: H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L21/324 ,  H01L21/306

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/3247 ,  H01L29/0669 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides some methods for forming at least two different nanowire structures with different diameters on one substrate. Since the diameter of the nanowire structure will influence the threshold voltage (Vt) and the drive currents of a nanowire field effect transistor, in this invention, at least two nanowire structures with different diameters can be formed on one substrate. Therefore, in the following steps, these nanowire structures can be applied in different nanowire field effect transistors with different Vt and drive currents. This way, the flexibility of the nanowire field effect transistors can be improved.

Abstract translation: 本发明提供了在一个基底上形成具有不同直径的至少两种不同纳米线结构的一些方法。 由于纳米线结构的直径将影响纳米线场效应晶体管的阈值电压（Vt）和驱动电流，所以在本发明中，可以在一个衬底上形成具有不同直径的至少两个纳米线结构。 因此，在以下步骤中，这些纳米线结构可以应用于具有不同Vt和驱动电流的不同纳米线场效应晶体管中。 这样，可以提高纳米线场效应晶体管的灵活性。