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    FIN SHAPED STRUCTURE AND METHOD OF FORMING THE SAME
    31.
    发明申请
    FIN SHAPED STRUCTURE AND METHOD OF FORMING THE SAME 有权
    FIN形状结构及其形成方法

    公开(公告)号：US20160141387A1

    公开(公告)日：2016-05-19

    申请号：US14541107

    申请日：2014-11-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： I-Ming Tseng ,  Rai-Min Huang ,  Tong-Jyun Huang ,  Kuan-Hsien Li ,  Chen-Ming Huang

    IPC: H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L21/308 ,  H01L29/10 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02

    CPC classification number: H01L29/66537 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

    Abstract: A fin shaped structure and a method of forming the same, wherein the method includes forming a fin structure on a substrate. Next, an insulation layer is formed on the substrate and surrounds the fin structure, wherein the insulation layer covers a bottom portion of the fin structure to expose an exposed portion of the fin structure protruded from the insulation layer. Then, a buffer layer is formed on the fin structure. Following this, a threshold voltage implantation process is performed to penetrate through the buffer layer after forming the insulation layer, to form a first doped region on the exposed portion of the fin structure.

    Abstract translation: 鳍状结构及其形成方法，其中，所述方法包括在基板上形成翅片结构。 接下来，在衬底上形成绝缘层并围绕鳍结构，其中绝缘层覆盖翅片结构的底部以暴露从绝缘层突出的鳍结构的暴露部分。 然后，在翅片结构上形成缓冲层。 接下来，在形成绝缘层之后，执行阈值电压注入工艺以穿透缓冲层，以在鳍结构的暴露部分上形成第一掺杂区域。

    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE
    32.
    发明申请
    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE 有权
    形成半导体结构的方法

    公开(公告)号：US20150147874A1

    公开(公告)日：2015-05-28

    申请号：US14088445

    申请日：2013-11-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Cheng Huang ,  I-Ming Tseng ,  Yu-Ting Li ,  Chun-Hsiung Wang ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  Po-Chao Tsao ,  Chien-Ting Lin ,  Shih-Fang Tzou

    IPC: H01L21/8234 ,  H01L21/265

    CPC classification number: H01L21/823431 ,  H01L21/265 ,  H01L21/3086 ,  H01L29/6681

    Abstract: The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin.

    Abstract translation: 本发明提供一种用于形成半导体结构的制造方法，其中首先设置基板，在基板上设置硬掩模，然后将硬掩模图案化以形成多个散热片硬掩模和多个虚拟 翅片硬掩模，然后进行图案转印处理，将翅片硬掩模和翅片硬掩模的图案转移到基板中，以形成多个翅片组和多个虚拟翅片。 每个假翅片设置在一个翅片组的端侧，并进行翅片切割处理，以去除每个假翅片。

    ELECTRICAL CONTACT
    33.
    发明申请
    ELECTRICAL CONTACT 审中-公开
    电气联系

    公开(公告)号：US20140225262A1

    公开(公告)日：2014-08-14

    申请号：US14261409

    申请日：2014-04-24

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： I-Ming Tseng ,  Tsung-Lung Tsai ,  Yi-Wei Chen

    IPC: H01L23/498

    CPC classification number: H01L23/49866 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823814 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An electrical contact includes a substrate, at least an insulation layer, a metal layer, a conductive layer, and a metal silicide layer. The substrate includes at least a silicon region. The insulation layer is disposed on the substrate and includes at least a contact hole exposing the silicon region. The metal layer is formed on the sidewalls and the bottom of the contact hole. The metal layer adjacent to the bottom surface is thinner than the metal layer on the sidewalls. The conductive layer covers the metal layer and fills up the contact hole. The metal silicide layer is adjacent to the bottom of the contact hole.

    Abstract translation: 电接触包括至少绝缘层，金属层，导电层和金属硅化物层的衬底。 衬底至少包括硅区域。 绝缘层设置在基板上，并且至少包括露出硅区域的接触孔。 金属层形成在接触孔的侧壁和底部上。 与底面相邻的金属层比侧壁上的金属层薄。 导电层覆盖金属层并填充接触孔。 金属硅化物层与接触孔的底部相邻。

    Semiconductor structure and method for forming the same
    34.
    发明授权
    Semiconductor structure and method for forming the same 有权

    公开(公告)号：US12284812B2

    公开(公告)日：2025-04-22

    申请号：US18636306

    申请日：2024-04-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Chien-Ting Lin

    IPC: H10B61/00 ,  G11C11/16 ,  H10N50/01 ,  H10N50/80

    Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

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