公开(公告)号：US20160378540A1

公开(公告)日：2016-12-29

申请号：US14751979

申请日：2015-06-26

Applicant: International Business Machines Corporation

Inventor： Fadi Y. Busaba ,  Michael K. Gschwind ,  Valentina Salapura ,  Eric M. Schwarz ,  Chung-Lung K. Shum

IPC: G06F9/46 ,  G06F9/48

CPC classification number: G06F9/467 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0637 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/4881 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/084 ,  G06F12/0842 ,  G06F13/1663 ,  G06F2212/1016 ,  G06F2212/314 ,  G06F2212/6042 ,  G06F2212/621

Abstract: Embodiments relate to multithreaded transactions. An aspect includes assigning a same transaction identifier (ID) corresponding to the multithreaded transaction to a plurality of threads of the multithreaded transaction, wherein the plurality of threads execute the multithreaded transaction in parallel. Another aspect includes determining one or more memory areas that are owned by the multithreaded transaction. Another aspect includes receiving a memory access request from a requester that is directed to a memory area that is owned by the transaction. Yet another aspect includes based on determining that the requester has a transaction ID that matches the transaction ID of the multithreaded transaction, performing the memory access request without aborting the multithreaded transaction.

Abstract translation: 实施例涉及多线程事务。 一个方面包括将与多线程事务相对应的相同事务标识符（ID）分配给多线程事务的多个线程，其中多个线程并行执行多线程事务。 另一方面包括确定由多线程事务拥有的一个或多个存储器区域。 另一方面包括从请求者接收指向由该事务拥有的存储区域的存储器访问请求。 另一方面包括基于确定请求者具有与多线程事务的事务ID匹配的事务ID，执行存储器访问请求而不中止多线程事务。

公开(公告)号：US20160371222A1

公开(公告)日：2016-12-22

申请号：US15184181

申请日：2016-06-16

Applicant: QUALCOMM Incorporated

Inventor： Shaul Yohai Yifrach ,  Amit Gil ,  James Lionel Panian ,  Ofer Rosenberg

IPC: G06F13/42 ,  G06F13/40 ,  G06F12/08

CPC classification number: G06F13/4282 ,  G06F12/0828 ,  G06F12/1441 ,  G06F13/4022 ,  G06F15/167 ,  G06F21/00 ,  G06F2212/621 ,  G06F2213/0026

Abstract: Coherency driven enhancements to a PCIe transaction layer are disclosed. In an exemplary aspect, a coherency agent is added to a PCIe system to support a relaxed consistency model for use of memory therein. In particular, endpoints can request ownership of portions of the memory to read from and write to the memory. The coherency agent assigns an address range including the requested portions. The requesting endpoint copies the contents of the memory corresponding to the assigned address range into local endpoint memory to perform read and write operations locally. The owning endpoint may provide an updated snapshot of the copied memory contents upon request. At completion of use of the copied memory contents, or upon request from the coherency agent, ownership of the address range reverts back to the root complex, and the endpoint sends the updated contents back to the address range in the system memory element.

Abstract translation: 公开了对PCIe事务层的一致性驱动增强。 在示例性方面，将一致性代理添加到PCIe系统以支持用于其中的存储器的松弛一致性模型。 特别地，端点可以请求存储器的部分的所有权从存储器读取和写入存储器。 一致性代理分配包括所请求部分的地址范围。 请求端点将对应于分配的地址范围的内存的内容复制到本地端点存储器中，以在本地执行读写操作。 所拥有的端点可以根据请求提供复制的存储器内容的更新的快照。 在完成使用复制的存储器内容时，或者根据来自一致性代理的请求，地址范围的所有权返回到根复合体，并且端点将更新的内容发送回系统存储器元件中的地址范围。

公开(公告)号：US20160357596A1

公开(公告)日：2016-12-08

申请号：US15240496

申请日：2016-08-18

Applicant: International Business Machines Corporation

Inventor： Fadi Y. Busaba ,  Harold W. Cain, III ,  Michael Karl Gschwind ,  Maged M. Michael ,  Valentina Salapura

IPC: G06F9/46 ,  G06F12/0817 ,  G06F12/084

CPC classification number: G06F9/467 ,  A63B69/18 ,  G06F12/0828 ,  G06F12/084 ,  G06F2212/314 ,  G06F2212/621

Abstract: A transactional memory system determines whether to pass control of a transaction to an about-to-run-out-of-resource handler. A processor of the transactional memory system determines information about an about-to-run-out-of-resource handler for transaction execution of a code region of a hardware transaction. The processor dynamically monitors an amount of available resource for the currently running code region of the hardware transaction. The processor detects that the amount of available resource for transactional execution of the hardware transaction is below a predetermined threshold level. The processor, based on the detecting, saves speculative state information of the hardware transaction, and executes the about-to-run-out-of-resource handler, the about-to-run-out-of-resource handler determining whether the hardware transaction is to be aborted or salvaged.

公开(公告)号：US09507628B1

公开(公告)日：2016-11-29

申请号：US14867148

申请日：2015-09-28

Applicant: International Business Machines Corporation

Inventor： Fadi Y. Busaba ,  Harold W. Cain, III ,  Michael Karl Gschwind ,  Valentina Salapura ,  Timothy J. Slegel

IPC: G06F9/46 ,  G06F13/16 ,  G06F13/42 ,  G06F9/50

CPC classification number: G06F9/467 ,  G06F3/0605 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0811 ,  G06F12/0828 ,  G06F12/0862 ,  G06F13/16 ,  G06F13/42 ,  G06F2212/283 ,  G06F2212/602 ,  G06F2212/621

Abstract: A computer-implemented method includes identifying two or more memory locations and referencing, by a memory access request, the two or more memory locations. The memory access request is a single action pursuant to a memory protocol. The computer-implemented method further includes sending the memory access request from one or more processors to a node and fetching, by the node, data content from each of the two or more memory locations. The computer-implemented method further includes packaging, by the node, the data content from each of the two or more memory locations into a memory package, and returning the memory package from the node to the one or more processors. A corresponding computer program product and computer system are also disclosed.

Abstract translation: 计算机实现的方法包括识别两个或更多个存储器位置，并且通过存储器访问请求来引用两个或多个存储器位置。 存储器访问请求是根据存储器协议的单个动作。 计算机实现的方法还包括将存储器访问请求从一个或多个处理器发送到节点并且由该节点从两个或多个存储器位置中的每一个获取数据内容。 计算机实现的方法还包括由节点将数据内容从两个或多个存储器位置中的每一个封装到存储器包中，以及将存储器包从该节点返回到一个或多个处理器。 还公开了相应的计算机程序产品和计算机系统。

公开(公告)号：US09483403B2

公开(公告)日：2016-11-01

申请号：US14306661

申请日：2014-06-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Guy L. Guthrie ,  Hien Minh Le ,  Jeffrey A. Stuecheli ,  Phillip G. Williams

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0828 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0864 ,  G06F12/0897 ,  G06F2212/314 ,  G06F2212/6032

Abstract: A technique for operating a memory system for a node includes interrogating, by a cache, an associated cache directory to determine whether a shared cache line to be installed in the cache is associated with an invalid global state in the cache. The invalid global state specifies that a version of the shared cache line has been intervened off-node. In response to the shared cache line being in the invalid global state the cache spawns a castout invalid global command for the shared cache line. The shared cache line is installed in the cache. A coherence state for the shared cache line is updated in the associated cache directory to indicate the shared cache line is shared.

Abstract translation: 用于操作用于节点的存储器系统的技术包括由高速缓存询问相关联的高速缓存目录，以确定要安装在高速缓存中的共享高速缓存行是否与高速缓存中的无效全局状态相关联。 无效的全局状态指定共享高速缓存行的版本已经在节点之外插入。 响应于共享高速缓存行处于无效全局状态，缓存为共享高速缓存行产生一个抛出无效的全局命令。 共享缓存行安装在缓存中。 在相关联的高速缓存目录中更新共享高速缓存行的一致性状态，以指示共享高速缓存行被共享。

公开(公告)号：US09465767B2

公开(公告)日：2016-10-11

申请号：US14931406

申请日：2015-11-03

Applicant: Texas Instruments Incorporated

Inventor： Kai Chirca ,  Matthew D Pierson ,  Daniel B Wu ,  Timothy D Anderson

IPC: G06F15/00 ,  G06F13/42 ,  G06F12/08 ,  G06F13/16 ,  H04L29/06 ,  G06F1/12

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.

公开(公告)号：US09465740B2

公开(公告)日：2016-10-11

申请号：US13860885

申请日：2013-04-11

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Harshavardhan Kaushikkar ,  Shinye Shiu

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0828 ,  G06F2212/1008 ,  G06F2212/507

Abstract: An apparatus for processing coherency transactions in a computing system is disclosed. The apparatus may include a request queue circuit, a duplicate tag circuit, and a memory interface unit. The request queue circuit may be configured to generate a speculative read request dependent upon a received read transaction. The duplicate tag circuit may be configured to store copies of tag from one or more cache memories, and to generate a kill message in response to a determination that data requested in the received read transaction is stored in a cache memory. The memory interface unit may be configured to store the generated speculative read request dependent upon a stall condition. The stored speculative read request may be sent to a memory controller dependent upon the stall condition. The memory interface unit may be further configured to delete the speculative read request in response to the kill message.

Abstract translation: 公开了一种用于处理计算系统中的一致性事务的装置。 该装置可以包括请求队列电路，复制标签电路和存储器接口单元。 请求队列电路可以被配置为根据所接收的读取事务来生成推测性读取请求。 重复标签电路可以被配置为存储来自一个或多个高速缓冲存储器的标签的副本，并且响应于所接收的读取事务中请求的数据被存储在高速缓冲存储器中的确定来生成杀死消息。 存储器接口单元可以被配置为根据失速条件来存储产生的推测性读取请求。 存储的推测性读取请求可以根据失速条件发送到存储器控制器。 存储器接口单元还可以被配置为响应于杀死消息来删除推测性读取请求。

公开(公告)号：US09430380B2

公开(公告)日：2016-08-30

申请号：US14312157

申请日：2014-06-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Guy L. Guthrie ,  Hugh Shen ,  Derek E. Williams

IPC: G06F12/08

CPC classification number: G06F12/08 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0828 ,  G06F12/0833 ,  G06F2212/283 ,  G06F2212/62

Abstract: In response to execution in a memory transaction of a transactional load instruction that speculatively binds to a value held in a store-through upper level cache, a processor core sets a flag, transmits a transactional load operation to a store-in lower level cache that tracks a target cache line address of a target cache line containing the value, monitors, during a core TM tracking interval, the target cache line address for invalidation messages from the store-in lower level cache until the store-in lower level cache signals that the store-in lower level cache has assumed responsibility for tracking the target cache line address, and responsive to receipt during the core TM tracking interval of an invalidation message indicating presence of a conflicting snooped operation, resets the flag. At termination of the memory transaction, the processor core fails the memory transaction responsive to the flag being reset.

公开(公告)号：US20160246721A1

公开(公告)日：2016-08-25

申请号：US14626913

申请日：2015-02-19

Applicant: QUALCOMM Incorporated

Inventor： Phil Joseph BOSTLEY, III ,  Jaya Prakash Subramaniam GANASAN

IPC: G06F12/08 ,  G06F9/46 ,  G06F9/455

CPC classification number: G06F12/0828 ,  G06F9/45558 ,  G06F9/466 ,  G06F12/0811 ,  G06F12/0833 ,  G06F2009/45587 ,  G06F2212/1028 ,  G06F2212/152 ,  G06F2212/283 ,  G06F2212/622 ,  Y02D10/13

Abstract: A method for controlling cache snoop and/or invalidate coherence traffic for specific caches based on transaction attributes is described. A memory management unit (MMU) determines one or more transaction attributes for a cache coherence transaction from a requesting processor. A routing module identifies a cachability domain and/or shareability domain based on the transaction attributes and routes the cache coherence transaction to one or more caches in the cachability domain and/or shareability domain. Instead of coherence traffic being routed to all caches on a coherence bus, coherence traffic is selectively routed based on transaction attributes such as an address space identifier (ASID), a virtual machine identifier (VMID), a secure bit (NS), a hypervisor identifier (HYP), etc.

Abstract translation: 描述了一种基于事务属性来控制缓存窥探和/或使特定高速缓存的相干流量无效的方法。 存储器管理单元（MMU）从请求处理器确定用于高速缓存一致性事务的一个或多个事务属性。 路由模块基于事务属性识别可访问域和/或可共享域，并将高速缓存一致性事务路由到可缓存域和/或可共享域中的一个或多个高速缓存。 代替一致性流量被路由到相干总线上的所有高速缓存，相干流量基于诸如地址空间标识符（ASID），虚拟机器标识符（VMID），安全位（NS），管理程序 标识符（HYP）等

公开(公告)号：US09396114B2

公开(公告)日：2016-07-19

申请号：US14849415

申请日：2015-09-09

Applicant: International Business Machines Corporation

Inventor： Michael T. Benhase ,  Lokesh M. Gupta ,  Matthew J. Kalos

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0828 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/121 ,  G06F2212/604 ,  G06F2212/622

Abstract: A controller receives a request to perform staging or destaging operations with respect to an area of a cache. A determination is made as to whether more than a threshold number of discard scans are waiting to be performed. The controller avoids satisfying the request to perform the staging or the destaging operations or a read hit with respect to the area of the cache, in response to determining that more than the threshold number of discard scans are waiting to be performed.