公开(公告)号：US20240362165A1

公开(公告)日：2024-10-31

申请号：US18771430

申请日：2024-07-12

Applicant: Huawei Cloud Computing Technologies Co., Ltd.

Inventor： Xiao Liu ,  Zhou Yu

IPC: G06F12/0817

CPC classification number: G06F12/0828 ,  G06F2212/621

Abstract: A computing device and a data processing method and system are provided. The computing device includes a central processing unit, at least one heterogeneous device, and a shared memory pool. The central processing unit is configured to: divide the shared memory pool into a plurality of memory spaces, store, in a first memory space in the plurality of memory spaces, first to-be-processed data that is provided by a client and that is associated with a service, and notify a first heterogeneous device of an address of the first to-be-processed data in the first memory space and a first operation that needs to be performed by the first heterogeneous device. The first heterogeneous device performs the first operation on the first to-be-processed data, and stores obtained first data in a second memory space.

公开(公告)号：US12079471B2

公开(公告)日：2024-09-03

申请号：US17875457

申请日：2022-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Brad Wu

IPC: G06F12/084 ,  G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/12 ,  G06F13/16 ,  G06F13/40 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F12/0846 ,  G06F12/0862

CPC classification number: G06F3/0604 ,  G06F3/0607 ,  G06F3/0632 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0607 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0855 ,  G06F12/0857 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/124 ,  G06F13/1642 ,  G06F13/1663 ,  G06F13/1668 ,  G06F13/4027 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F12/0833 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0862 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1048 ,  G06F2212/304 ,  G06F2212/452 ,  G06F2212/6024 ,  G06F2212/657

Abstract: A device includes an arbiter circuit configured to receive a first request for a resource. The first request is associated with a first credit cost. The arbiter circuit is further configured to receive a second request for the resource. The second request is associated with a second credit cost. The arbiter circuit is further configured to select the first request for the resource as an arbitration winner. The arbiter circuit is further configured to decrement a number of available credits associated with the resource by the first credit cost. The arbiter circuit is further configured to, in response to the number of available credits associated with the resource falling to a lower credit threshold, wait until the number of available credits associated with the resource reaches an upper credit threshold to select an additional arbitration winner for the resource.

公开(公告)号：US20240281278A1

公开(公告)日：2024-08-22

申请号：US18654035

申请日：2024-05-03

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/448 ,  G06F9/48 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/121 ,  G06F13/16

CPC classification number: G06F9/467 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/3867 ,  G06F9/4498 ,  G06F9/4881 ,  G06F9/544 ,  G06F11/3037 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/1668 ,  G06F12/0804 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/621

Abstract: A method includes receiving, by a first stage in a pipeline, a first transaction from a previous stage in pipeline; in response to first transaction comprising a high priority transaction, processing high priority transaction by sending high priority transaction to a buffer; receiving a second transaction from previous stage; in response to second transaction comprising a low priority transaction, processing low priority transaction by monitoring a full signal from buffer while sending low priority transaction to buffer; in response to full signal asserted and no high priority transaction being available from previous stage, pausing processing of low priority transaction; in response to full signal asserted and a high priority transaction being available from previous stage, stopping processing of low priority transaction and processing high priority transaction; and in response to full signal being de-asserted, processing low priority transaction by sending low priority transaction to buffer.

公开(公告)号：US20240241830A1

公开(公告)日：2024-07-18

申请号：US18413211

申请日：2024-01-16

Applicant: Akeana, Inc.

Inventor： Sanjay Patel ,  Yogesh Shamkant Thombre

IPC: G06F12/0817 ,  G06F12/0868 ,  G06F12/0873

CPC classification number: G06F12/0828 ,  G06F12/0868 ,  G06F12/0873

Abstract: Techniques for cache management based on cache management using memory queues are disclosed. A plurality of processor cores is accessed. The plurality of processor cores comprises a coherency domain. Two or more processor cores within the plurality of processor cores generate read operations for a common memory structure coupled to the plurality of processor cores. Coherency for the coherency domain is managed using a compute coherency block (CCB). The CCB includes a memory queue for controlling transfer of cache lines determined by the CCB. The memory queue includes an evict queue and a miss queue. Snoop requests are generated by the CCB. The snoop requests correspond to entries in the memory queue. Cache lines are transferred between the CCB and a bus interface unit. The transferring is controlled by the memory queue. The bus interface unit controls memory accesses.

公开(公告)号：US11983115B2

公开(公告)日：2024-05-14

申请号：US18166244

申请日：2023-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Heehyun Nam ,  Jaeho Shin ,  Hyodeok Shin ,  Younggeon Yoo ,  Younho Jeon ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F12/0817 ,  G06F3/06 ,  G06F12/0862

CPC classification number: G06F12/0828 ,  G06F3/0622 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0862 ,  G06F2212/602 ,  G06F2212/621

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

公开(公告)号：US20240143506A1

公开(公告)日：2024-05-02

申请号：US17974881

申请日：2022-10-27

Applicant: Synopsys, Inc.

Inventor： Karthik THUCANAKKENPALAYAM SUNDARARAJAN

IPC: G06F12/0817 ,  G06F3/06

CPC classification number: G06F12/0828 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/621

Abstract: A system and method service memory transaction requests by receiving a memory transaction request for a first memory line from a first processor core of processor cores of a processing system. A second processor core of the processor cores is determined to include the first memory line in a shared state. Data of the first memory line is communicated from the second processor core to the first processor core based on determining that the second processor core comprises the first memory line in a shared state.

公开(公告)号：US11947994B2

公开(公告)日：2024-04-02

申请号：US16367910

申请日：2019-03-28

Applicant: SAP SE

Inventor： Thomas Legler

IPC: G06F9/46 ,  G06F9/52 ,  G06F12/0817 ,  G06F16/25

CPC classification number: G06F9/467 ,  G06F9/52 ,  G06F12/0828 ,  G06F16/25

Abstract: A method may include determining a threshold quantity of attempts to optimistically perform a first transaction operating data stored in a database. The threshold quantity of attempts may be determined based on an expected workload of the first transaction and/or a workload at the database. The first transaction may be performed optimistically including by tracking cache lines accessed by the first transaction and detecting, based on a second transaction writing to a cache line accessed by the first transaction, a conflict between the first transaction and the second transaction. If the first transaction is not successful performed after the threshold quantity of attempts to optimistically perform the first transaction, the first transaction may be performed in a fallback mode including by acquiring a lock to prevent the second transaction from accessing a same data in the database as the first transaction. Related systems and articles of manufacture are also provided.

公开(公告)号：US11947458B2

公开(公告)日：2024-04-02

申请号：US16048180

申请日：2018-07-27

Applicant: VMware LLC

Inventor： Irina Calciu ,  Jayneel Gandhi ,  Aasheesh Kolli ,  Pratap Subrahmanyam

IPC: G06F12/0817

CPC classification number: G06F12/0828 ,  G06F2212/152

Abstract: A device is connected via a coherence interconnect to a CPU with a cache. The device monitors cache coherence events via the coherence interconnect, where the cache coherence events relate to the cache of the CPU. The device also includes a buffer that can contain representations, such as addresses, of cache lines. If a coherence event occurs on the coherence interconnect indicating that a cache line in the CPU's cache is dirty, then the device is configured to add an entry to the buffer to record the dirty cache line.

公开(公告)号：US20240086065A1

公开(公告)日：2024-03-14

申请号：US18512261

申请日：2023-11-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai CHIRCA ,  Timothy David ANDERSON

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0855 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/12 ,  G06F13/16 ,  G06F13/40 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27

CPC classification number: G06F3/0604 ,  G06F3/0607 ,  G06F3/0632 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0607 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0855 ,  G06F12/0857 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/124 ,  G06F13/1642 ,  G06F13/1663 ,  G06F13/1668 ,  G06F13/4027 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F12/0846 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/304 ,  G06F2212/452 ,  G06F2212/657

Abstract: Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.

公开(公告)号：US11892949B2

公开(公告)日：2024-02-06

申请号：US18154204

申请日：2023-01-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christian Zoellin ,  Christian Jacobi ,  Chung-Lung K. Shum ,  Martin Recktenwald ,  Anthony Saporito ,  Aaron Tsai

IPC: G06F12/0817 ,  G06F12/0831 ,  G06F12/0842

CPC classification number: G06F12/0828 ,  G06F12/0822 ,  G06F12/0833 ,  G06F12/0842 ,  G06F2212/1024

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.