公开(公告)号：US20020135104A1

公开(公告)日：2002-09-26

申请号：US10026382

申请日：2001-12-20

Inventor： Jesse Pedigo ,  Timothy Meyer

IPC: B23K031/02

CPC classification number: H05K3/1233 ,  H05K3/0094 ,  H05K3/4053 ,  H05K3/4069 ,  H05K2201/0959 ,  H05K2201/10204 ,  H05K2203/0126 ,  H05K2203/0139 ,  H05K2203/0156 ,  H05K2203/0182 ,  H05K2203/0554 ,  H05K2203/1105

Abstract: A filling system includes a pressurized source of fill material and a pressure fill head wherein the fill head also includes a heating element positioned so as to transfer heat to fill material passing through the fill head. A method of filling holes using a fill material passing through a pressure fill head includes the steps of causing fill material to enter the fill head, modifying the viscosity of the fill material while it is within the fill head, and causing the modified viscosity fill material to exit the fill head and enter at least one hole.

Abstract translation: 填充系统包括加压填充源和压力填充头，其中填充头还包括加热元件，其被定位成传递热量以填充通过填充头的材料。 使用通过压力填充头的填充材料填充孔的方法包括以下步骤：使填充材料进入填充头，在填充头内部改变填充材料的粘度，并且使改性粘度填充材料 退出填充头并进入至少一个孔。

公开(公告)号：US5978093A

公开(公告)日：1999-11-02

申请号：US895766

申请日：1997-07-17

Applicant: Steve Abrahamson

Inventor： Steve Abrahamson

IPC: H05K1/02 ,  H05K3/30 ,  H05K13/04 ,  G01B11/00 ,  G01J1/02 ,  G06K9/00 ,  H01L21/66

CPC classification number: H05K3/305 ,  H05K13/0465 ,  H05K1/0269 ,  H05K2201/0108 ,  H05K2201/10204 ,  H05K2203/161 ,  H05K2203/162 ,  Y02P70/613

Abstract: A method and apparatus for calibrating surface mounting processes in the manufacturing of printed circuit board assemblies. In one embodiment of a method in accordance with the invention, a test pad of adhesive is deposited onto a substrate, and then a test module is mounted to the substrate at the test pad. The test module is representative of an electrical component that is to be mounted to a printed circuit board, and the test module is mounted to the substrate in a manner in which the electrical component is to be mounted to a printed circuit board. After the test module is mounted to the substrate, the profile of the test pad is detected through the substrate and/or the test module to determine whether the test pad contacts enough of the test module to sufficiently adhere the test module to the substrate without interfering with the terminals of the test module. Accordingly, this embodiment of the inventive method provides an indication or estimate of the desired volume of an adhesive pad to mount a specific component to a PCB.

Abstract translation: 一种用于校准印刷电路板组件制造中的表面安装工艺的方法和装置。 在根据本发明的方法的一个实施例中，将粘合剂测试垫沉积到基底上，然后在测试垫处将测试模块安装到基底上。 测试模块代表要安装到印刷电路板的电气部件，并且测试模块以将电气部件安装到印刷电路板的方式安装到基板。 在将测试模块安装到衬底之后，通过衬底和/或测试模块检测测试焊盘的轮廓，以确定测试焊盘是否接触足够的测试模块，以充分地将测试模块粘附到衬底而不干扰 与测试模块的终端。 因此，本发明方法的该实施例提供了将特定部件安装到PCB的粘合垫的期望体积的指示或估计。

公开(公告)号：US5626713A

公开(公告)日：1997-05-06

申请号：US366615

申请日：1994-12-30

Applicant: Shoji Yamaguchi ,  Akira Yamada ,  Yasuo Furuhashi ,  Fumiaki Baba

Inventor： Shoji Yamaguchi ,  Akira Yamada ,  Yasuo Furuhashi ,  Fumiaki Baba

IPC: H05K3/38 ,  B29C33/68 ,  B29C37/00 ,  H05K1/18 ,  H05K3/46 ,  B32B35/00

CPC classification number: B29C37/005 ,  B32B37/0023 ,  B32B37/04 ,  B32B37/1284 ,  B32B37/26 ,  H05K3/4697 ,  B29C33/68 ,  B29L2031/3425 ,  B32B2457/08 ,  H05K1/183 ,  H05K2201/0129 ,  H05K2201/10204 ,  H05K2203/063 ,  H05K2203/1147 ,  Y10T156/16

Abstract: An apparatus for producing a multi-layer printed circuit board. The printed circuit board includes a bottom layer board, a hole board, and an adhesive sheet between the bottom layer board and the hole board. The printed circuit board is heated so that adhesive sheet bonds the bottom layer board to the hole board. A mold release sheet and a thermoplastic resin sheet begins to soften at a temperature lower than the melting temperature of the adhesive. A contraction control member controls contraction when the thermoplastic resin sheet cools.

Abstract translation: 一种多层印刷电路板的制造装置。 印刷电路板包括底层板，孔板和底层板和孔板之间的粘合片。 印刷电路板被加热，使得粘合片将底层板粘合到孔板。 脱模片和热塑性树脂片在低于粘合剂的熔融温度的温度下开始软化。 当热塑性树脂片材冷却时，收缩控制构件控制收缩。

公开(公告)号：US5296082A

公开(公告)日：1994-03-22

申请号：US853115

申请日：1992-03-18

Applicant: Isamu Kubo

Inventor： Isamu Kubo

IPC: B26F1/02 ,  B25B1/24 ,  H05K3/00 ,  H05K13/00 ,  B32B31/14

CPC classification number: B25B1/241 ,  H05K3/005 ,  H05K2201/10204 ,  H05K3/0047 ,  Y10S269/90 ,  Y10S269/903 ,  Y10S83/942

Abstract: A mold used in producing printed wiring board is disclosed. The mold comprises upper dies and lower dies for sandwiching a printed wiring board therebetween, thereby performing drilling, punching or the like, one of said upper dies and lower dies having a press surface which is provided with concave or convex portions for absorbing steps caused by forming a printed wiring circuit on the printed wiring board.

Abstract translation: 公开了用于制造印刷电路板的模具。 模具包括用于将印刷电路板夹在其间的上模和下模，从而执行钻孔，冲孔等，所述上模和下模中的一个具有压制表面，所述压模表面设置有凹部或凸部，用于吸收由 在印刷电路板上形成印刷布线电路。

公开(公告)号：US5196087A

公开(公告)日：1993-03-23

申请号：US717341

申请日：1991-06-18

Applicant: Robert Q. Kerns

Inventor： Robert Q. Kerns

IPC: H05K3/00 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/4638 ,  H05K3/0002 ,  H05K2201/10204 ,  H05K2203/056 ,  H05K2203/162 ,  H05K3/0005 ,  H05K3/427 ,  H05K3/4611

Abstract: A multi-layer printed circuit board is disclosed as having more layers and greater accuracy in the conductive traces of those layers than has been previously possible. Using the disclosed method, multi-layer printed circuit boards can be built having a conductive path width of 0.5 mils (0.0127 mm) and spacing between such conductive traces of 0.5 mils (0.0127 mm). The method enables multi-layer boards to be created having more than eight layers, and still maintaining the desired 0.5 mil conductive path width and spacing. The enhanced accuracy and increased number of layers is made possible by use of adjustments to customer-supplied art work based upon evaluation of test pieces made early in the procedure. By use of the disclosed method, multi-layer printed circuit boards can be built having a high density of coaxial cable equivalents and tuned wave guide equivalents. An apparatus is also disclosed which connects the coaxial cable equivalents and tuned wave guide equivalents from one multi-layer printed circuit board to a second multi-layer printed circuit board.

Abstract translation: 公开了一种多层印刷电路板，其在这些层的导电迹线中具有比之前可能的更多的层和更高的精度。 使用所公开的方法，可以构建具有0.5密耳（0.0127mm）的导电路径宽度和0.5密耳（0.0127mm）的这种导电迹线之间的间隔的多层印刷电路板。 该方法使得能够创建具有多于8层的多层板，并且仍然保持期望的0.5密耳导电路径宽度和间隔。 通过基于对程序早期制作的试件的评估，对客户提供的艺术作品进行调整，可以提高精度和增加层数。 通过使用所公开的方法，可以构建具有高密度同轴电缆等效物和调谐波导等效物的多层印刷电路板。 还公开了将同轴电缆等效物和调谐波导等效物从一个多层印刷电路板连接到第二多层印刷电路板的装置。

公开(公告)号：US4790694A

公开(公告)日：1988-12-13

申请号：US916779

申请日：1986-10-09

Applicant: John W. Wilent ,  Robert F. Benson ,  Robert A. Sparks

Inventor： John W. Wilent ,  Robert F. Benson ,  Robert A. Sparks

IPC: B23B49/00 ,  H05K3/00 ,  H05K3/46 ,  B23C3/00

CPC classification number: H05K3/4638 ,  H05K2201/09918 ,  H05K2201/10204 ,  H05K3/0008 ,  H05K3/0047 ,  H05K3/4611 ,  Y10T408/03 ,  Y10T408/08 ,  Y10T408/21 ,  Y10T83/178

Abstract: A method and apparatus for optimizing the drilling position of a multi-layer printed circuit board prior to drilling. A template having precisely located target holes and fixture reference marks provides initial coordinate reference information for multi-layer printed circuit boards to be inspected by x radiation. Each board is processed by insertion into a holding fixture, examination of four quadrant target areas using x-ray sources and detectors, digitization of the target area images in each quadrant, and computaton of the optimum board position in a follow-on drilling apparatus. After optimization, three reference holes are punched along one edge of the board to provide accurate fiducial positioning marks when the board is placed in the drilling apparatus.

Abstract translation: 一种用于在钻孔之前优化多层印刷电路板的钻孔位置的方法和装置。 具有精确定位的目标孔和夹具参考标记的模板提供了要被x辐射检查的多层印刷电路板的初始坐标参考信息。 每个板通过插入固定夹具进行处理，使用X射线源和检测器检查四个象限目标区域，在每个象限中对目标区域图像进行数字化，以及在后续钻孔设备中计算最佳板位置。 优化后，沿着板的一个边缘冲切三个参考孔，当板放置在钻孔装置中时，提供准确的基准定位标记。

公开(公告)号：US20240292544A1

公开(公告)日：2024-08-29

申请号：US18528973

申请日：2023-12-05

Applicant: DAEDUCK ELECTRONICS CO., LTD.

Inventor： Seon-Kyu CHANG ,  Hee-Il RYU

IPC: H05K3/30 ,  H05K1/18 ,  H05K3/02

CPC classification number: H05K3/305 ,  H05K1/181 ,  H05K3/022 ,  H05K2201/10204

Abstract: The present invention discloses a fabrication method of thick-walled printed circuit board PCB), especially the packaging substrate for mounting thin wafer level components on the PCB substrate. The present invention provides a first embodiment of inserting a dummy at the circuit board manufacturing stage and a second embodiment of adjusting the thickness by inserting a dummy at the wafer processing stage.

公开(公告)号：US20240032208A1

公开(公告)日：2024-01-25

申请号：US18115871

申请日：2023-03-01

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Tae Hong MIN ,  Eun Su KWON

IPC: H05K3/46 ,  H05K1/03 ,  H05K3/40 ,  H05K3/12

CPC classification number: H05K3/4626 ,  H05K1/036 ,  H05K3/4007 ,  H05K3/1258 ,  H05K2203/049 ,  H05K2203/176 ,  H05K2201/10204

Abstract: A printed circuit board includes a first build-up insulating layer; an interconnect structure buried in an upper side of the first build-up insulating layer and including one or more insulating layers, one or more wiring layers, and one or more via layers; an adhesive disposed between an upper surface of the first build-up insulating layer and an upper surface of the interconnect structure, and having an upper surface exposed from the upper surface of the first build-up insulating layer; and a metal bump including a via portion penetrating the adhesive and a protrusion protruding to the upper surface of the adhesive.

公开(公告)号：US20190037686A1

公开(公告)日：2019-01-31

申请号：US15658717

申请日：2017-07-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James A. BUSBY ,  John R. DANGLER ,  Michael J. FISHER ,  David C. LONG

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/11 ,  H05K1/18 ,  H05K5/02 ,  G01N27/04 ,  G06F21/87

CPC classification number: H05K1/0275 ,  G01N27/045 ,  G06F21/86 ,  G06F21/87 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K1/181 ,  H05K5/0208 ,  H05K2201/10151 ,  H05K2201/10204 ,  H05K2201/10371 ,  H05K2201/10522

Abstract: Tamper-respondent assemblies and methods of fabrication are provided which include at least one tamper-respondent sensor and a detector. The at least one tamper-respondent sensor includes conductive lines which form, at least in part, at least one tamper-detect network of the tamper-respondent sensor(s). In addition, the tamper-respondent sensor(s) includes at least one interconnect element associated with one or more conductive lines of the conductive lines forming, at least in part, the tamper-detect network(s). The interconnect element(s) includes at least one interconnect characteristic selected to facilitate obscuring a circuit lay of the at least one tamper-detect network. In operation, the detector monitors the tamper-detect network(s) of the tamper-respondent sensor(s) for a tamper event.

公开(公告)号：US20180042147A1

公开(公告)日：2018-02-08

申请号：US15488024

申请日：2017-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-ju MUN ,  Keon KUK ,  Ji-woon YEOM

IPC: H05K9/00 ,  H05K1/18

CPC classification number: H05K1/182 ,  B05D1/26 ,  B05D7/50 ,  H01L23/552 ,  H01L2224/16227 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K9/0024 ,  H05K2201/09972 ,  H05K2201/10204 ,  H05K2203/0126

Abstract: An electromagnetic interference (EMI) shielding structure and a manufacturing method thereof are provided. The EMI shielding structure includes a shielding dam provided on a printed circuit board, the shielding dam forming a closed loop that defines a periphery of adjacent shielding regions of the printed circuit board; an insulating member that is provided on the adjacent shielding regions within the shielding dam, the insulating member covering circuit devices provided in the adjacent shielding regions; and a shielding member that covers an upper surface of the insulating member, wherein the shielding dam includes a border portion surrounding the adjacent shielding regions, and a partition portion disposed between the adjacent shielding regions and within the border portion.