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31.
公开(公告)号:US20190196909A1
公开(公告)日:2019-06-27
申请号:US16289257
申请日:2019-02-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sompong Paul Olarig , David Schwaderer , Ramdas P. Kachare
CPC classification number: G06F11/1084 , G06F11/085 , G06F11/1008 , G06F11/1076 , G06F11/108 , G06F11/1088 , G06F11/1092 , G06F11/1096 , G06F11/1469 , G06F11/201 , G06F11/2012 , G06F11/2087 , G06F2201/84
Abstract: A system and method for providing erasure code protection across multiple storage devices. A data switch in a storage system connects a plurality of storage devices to a remote host. Each storage device is also connected to a controller, e.g., a baseboard management controller. During normal operation, read and write commands from the remote host are sent to respective storage devices through the data switch. When a write command is executed, the storage device executing the command sends a copy of the data to the controller, which generates and stores erasure codes, e.g., on a storage device that is dedicated to the storage of erasure codes, and invisible to the remote host. When a device fails or is removed, the controller reconfigures the data switch to redirect all traffic addressed to the failed or absent storage device to the controller, and the controller responds to host commands in its stead.
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公开(公告)号:US20190171622A1
公开(公告)日:2019-06-06
申请号:US16203008
申请日:2018-11-28
Applicant: NEC Laboratories America, Inc.
Inventor: Bo Zong , Jianwu Xu , Haifeng Chen
IPC: G06F16/17 , G06K9/62 , G06F11/08 , G06F16/9038 , G06F16/14
Abstract: Systems and methods for system event searching based on heterogeneous logs are provided. A system can include a processor device operatively coupled to a memory device wherein the processor device is configured to mine a variety of log patterns from various of heterogeneous logs to obtain known-event log patterns and unknown-event log patterns, as well as to build a weighted vector representation of the log patterns. The processor device is also configured to evaluate a similarity between the vector representation of the unknown-event and known-event log patterns, identify a known event that is most similar to an unknown event to troubleshoot system faults based on past actions for similar events to improve an operation of a computer system.
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公开(公告)号:US10289564B2
公开(公告)日:2019-05-14
申请号:US15741704
申请日:2015-07-08
Applicant: HITACHI, LTD.
Inventor: Yukari Hatta , Norimitsu Hayakawa , Takao Totsuka , Toshiomi Moriki , Satoshi Kinugawa
Abstract: A computer on which OSs run is coupled to the storage apparatus, the OSs include a first OS controlling access to the storage apparatus and a second OS generating a virtual computer. A logically divided computer resources are allocated to the first OS and the second OS respectively. A third OS for executing an application runs on the virtual computer. The second OS has a shared region management part managing a shared region that is a memory region used for communication between the application and the first OS. The third operating system has an agent requesting the second operating system to secure the shared region based on a request from the application and mapping the secured shared region to a guest virtual address space.
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公开(公告)号:US10237281B2
公开(公告)日:2019-03-19
申请号:US15221731
申请日:2016-07-28
Applicant: International Business Machines Corporation
Inventor: Gary W. Grube , Jason K. Resch
Abstract: A method for execution in a dispersed storage network operates to determine one or more slice names of one or more slices and determine whether to establish a new access policy corresponding to the one or more slices. When the new access policy is to be established, the method determines a timestamp; determines a new access policy; and sends the new access policy and the timestamp to one or more storage units that store the one or more slices.
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公开(公告)号:US20190073259A1
公开(公告)日:2019-03-07
申请号:US15839521
申请日:2017-12-12
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor: Minghai Qin , Dejan Vucinic , Chao Sun
Abstract: Disclosed include a device and a method for storing a neural network. The device includes a plurality of memory cells configured to store weights of the neural network. The plurality of memory cells may include one or more faulty cells. The device further includes a processor coupled to the plurality of memory cells. The processor is configured to construct the neural network based on a structure of the neural network and a subset of the weights stored by the plurality of memory cells. The subset of the weights may exclude another subset of the weights stored by one or more memory cells comprising the one or more faulty cells.
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公开(公告)号:US10216929B2
公开(公告)日:2019-02-26
申请号:US15084533
申请日:2016-03-30
Applicant: Infineon Technologies AG
Inventor: Benedikt Driessen , Steffen Sonnekalb
Abstract: A chip is provided having processing circuits, each processing circuit configured to process a data vector to be stored according to a multiplication of the vector by a processing matrix, the sum of the processing matrices corresponding to the non-unit-matrix part of a generator matrix of a predetermined linear code in reduced form, a summing circuit to sum the results of the processing operations of the data vector, a storage circuit to store the data vector to be stored together with the sum of the generated results as one data word in a memory, a read-out circuit to read the stored data word out of the memory, and a decoding circuit to check whether the data word read out is a valid code word of the linear code and to output an error signal if the data word is not a valid code word of the linear code.
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公开(公告)号:US10199122B2
公开(公告)日:2019-02-05
申请号:US15852678
申请日:2017-12-22
Applicant: Everspin Technologies Inc.
Inventor: Thomas Andre , Jon Slaughter , Dimitri Houssameddine , Syed M. Alam
Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
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公开(公告)号:US10120924B2
公开(公告)日:2018-11-06
申请号:US14543507
申请日:2014-11-17
Applicant: Akamai Technologies, Inc.
Inventor: Kai C Wong , Philip A Lisiecki , Sung Chiu
Abstract: A data storage system with quorum-based commits sometimes experiences replica failure, due to unavailability of a replica-hosting node, for example. Described herein are methods and systems for improving data persistence and availability in a distributed data store where data is stored in a plurality of shards and a given shard is replicated across a plurality of nodes so as to create a plurality of replicas, and a quorum of replicas is needed for access to the given shard. Among other things, the methods and systems generally involve determining whether to quarantine or delete unavailable replicas in a given shard, and how to handle purge requests related to the shard when there are quarantined replicas.
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公开(公告)号:US10108484B2
公开(公告)日:2018-10-23
申请号:US15346486
申请日:2016-11-08
Applicant: International Business Machines Corporation
Inventor: Asimuddin Kazi , Jason K. Resch
IPC: G06F11/08 , G06F11/10 , G06F3/06 , H03M13/05 , H03M13/00 , H03M13/37 , G06F11/00 , H03M13/09 , H03M13/15
Abstract: A method includes determining a root cause for a rebuilding request of an encoded data slice of a set of encoded data slices, where the rebuilding request includes a slice name of the encoded data slice corresponding to a slice error. The method further includes establishing a pricing level as a user pricing level when the root cause is a user-centric root cause, and establishing the pricing level as a non-user pricing level when the root cause is a non-user-centric root cause. The method further includes facilitating the rebuilding of the encoded data slice, and generating billing information for the rebuilding based on the pricing level.
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公开(公告)号:US10108469B2
公开(公告)日:2018-10-23
申请号:US14803051
申请日:2015-07-18
Applicant: Renesas Electronics Corporation
Inventor: Naoki Mitsuishi
Abstract: A microcomputer includes a plurality of functional blocks that exchange information with each other. A nonvolatile memory can rewrite information stored therein and first data has been written therein in advance. A central processing unit processes information read from the nonvolatile memory or writes information to the nonvolatile memory. An abnormality detecting unit detects an abnormality in exchange of data between the plurality of functional blocks. A nonvolatile memory checking unit reads the first data from the nonvolatile memory when the abnormality detecting unit has detected an abnormality, compares the first data with second data indicating the content of the first data when written to the nonvolatile memory, and detects an abnormality in the nonvolatile memory when a result of the comparison shows that the first data is not identical to the second data.
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