公开(公告)号：US20180083045A1

公开(公告)日：2018-03-22

申请号：US15267646

申请日：2016-09-16

Applicant: International Business Machines Corporation

Inventor： Effendi Leobandung

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/08 ,  H01L21/02 ,  H01L29/161 ,  H01L29/201 ,  H01L29/06 ,  H01L29/78 ,  H01L21/3105

CPC classification number: H01L27/1211 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/30612 ,  H01L21/31051 ,  H01L21/823418 ,  H01L21/845 ,  H01L29/0669 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/201 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for forming a semiconductor device. It includes forming fin structures on a substrate, where the fin structure defines source and drain regions. It also includes forming a gate stack in contact with the fin structure, depositing an insulator on the substrate, and applying an etching process to remove portions of the insulator to form a trench to the source region. It also includes implanting a damaged epitaxial material into the trench and to the source regions, and applying a second etching process to remove portions of the insulator to form a trench in the insulator to the drain regions. Finally, the method includes growing an epitaxial junction material over the source and drain regions, and depositing a metal over the substrate.

公开(公告)号：US20180034369A1

公开(公告)日：2018-02-01

申请号：US15713937

申请日：2017-09-25

Applicant: International Business Machines Corporation

Inventor： Hariklia Deligianni ,  Devendra K. Sadana ,  Edmund J. Sprogis ,  Naigang Wang

IPC: H02M3/158 ,  H01L21/762 ,  H01L21/84 ,  H01L23/535 ,  H01L29/201 ,  H01L27/12 ,  H01L21/768

CPC classification number: H02M3/158 ,  H01L21/7624 ,  H01L21/76243 ,  H01L21/76895 ,  H01L21/8258 ,  H01L21/84 ,  H01L23/5227 ,  H01L23/535 ,  H01L24/13 ,  H01L27/085 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/201 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/131 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/19104 ,  H02M3/00 ,  Y02B70/1483 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Fully integrated, on-chip DC-DC power converters are provided. In one aspect, a DC-DC power converter includes: a SOI wafer having a SOI layer separated from a substrate by a buried insulator, wherein the SOI layer and the buried insulator are selectively removed from at least one first portion of the SOI wafer, and wherein the SOI layer and the buried insulator remain present in at least one second portion of the SOI wafer; at least one GaN transistor formed on the substrate in the first portion of the SOI wafer; at least one CMOS transistor formed on the SOI layer in the second portion of the SOI wafer; a dielectric covering the GaN and CMOS transistors; and at least one magnetic inductor formed on the dielectric. A method of forming a fully integrated DC-DC power converter is also provided.

公开(公告)号：US09882042B2

公开(公告)日：2018-01-30

申请号：US14657704

申请日：2015-03-13

Applicant: NGK INSULATORS, LTD.

Inventor： Yoshitaka Kuraoka ,  Mikiya Ichimura ,  Makoto Iwai

IPC: H01L21/02 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/10 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207

CPC classification number: H01L29/7787 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/02581 ,  H01L21/0262 ,  H01L29/1029 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: Provided are a group 13 nitride composite substrate allowing for the production of a semiconductor device suitable for high-frequency applications while including a conductive GaN substrate, and a semiconductor device produced using this substrate. The group 13 nitride composite substrate includes a base material of an n-conductivity type formed of GaN, a base layer located on the base material, being a group 13 nitride layer having a resistivity of 1×106 Ω·cm or more, a channel layer located on the base layer, being a GaN layer having a total impurity density of 1×1017/cm3 or less, and a barrier layer that is located on the channel layer and is formed of a group 13 nitride having a composition AlxInyGa1−x−yN (0≦x≦1, 0≦y≦1).

公开(公告)号：US09881921B2

公开(公告)日：2018-01-30

申请号：US15483286

申请日：2017-04-10

Applicant: International Business Machines Corporation

Inventor： Lukas Czornomaz ,  Veeresh Vidyadhar Deshpande ,  Vladimir Djara ,  Jean Fompeyrine

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/201 ,  H01L29/161 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L29/20 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8232

CPC classification number: H01L27/0922 ,  H01L21/0206 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/20 ,  H01L29/201 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including SixGe1-x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.

公开(公告)号：US09871117B2

公开(公告)日：2018-01-16

申请号：US15062007

申请日：2016-03-04

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Uday Shah ,  Roza Kotlyar ,  Charles C. Kuo

IPC: H01L31/072 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/205 ,  H01L29/739 ,  H01L29/749 ,  H01L21/02 ,  H01L21/306 ,  H01L29/49 ,  H01L29/161 ,  H01L29/201 ,  H01L29/08

CPC classification number: H01L29/66666 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4983 ,  H01L29/66356 ,  H01L29/66363 ,  H01L29/7391 ,  H01L29/749 ,  H01L29/7827 ,  H01L29/7848

Abstract: Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.

公开(公告)号：US09865508B2

公开(公告)日：2018-01-09

申请号：US15337225

申请日：2016-10-28

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L27/01 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/306 ,  H01L21/283 ,  H01L21/311 ,  H01L27/092 ,  H01L29/06 ,  H01L29/201 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L21/823807 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0226 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/823814 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/201 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers of a first and a second material in a stack on a substrate; forming a first trench(es) and a second trench(es) in the stack; laterally etching the layer of the second material selectively within the first trench(es) to form first cavities in the layer; growing a first epitaxial material within the first trench(es) filling the first cavities; laterally etching the layer of the second material selectively within the second trench(es) to form second cavities in the layer; growing a second epitaxial material within the second trench(es) filling the second cavities, wherein the first epitaxial material in the first cavities and the second epitaxial material in the second cavities are the hybrid nanowires. A nanowire FET device and method for formation thereof are also provided.

公开(公告)号：US20170323946A1

公开(公告)日：2017-11-09

申请号：US15656480

申请日：2017-07-21

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz GARDNER ,  Seung Hoon SUNG ,  Robert S. Chau

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/78 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/201 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L21/285 ,  H01L21/283 ,  H01L29/80

CPC classification number: H01L29/2003 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/201 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/802

Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

公开(公告)号：US20170213825A1

公开(公告)日：2017-07-27

申请号：US15397123

申请日：2017-01-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： SIVANANDA K. KANAKASABAPATHY ,  FEE LI LIE ,  ERIC MILLER ,  STUART A. SIEG

IPC: H01L27/088 ,  H01L21/308 ,  H01L29/66 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/201 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/201 ,  H01L29/6653 ,  H01L29/66545

Abstract: Provided herein is a multi-channel finFET having a plurality of fins prepared by a process. The process includes forming a series of mandrels on hard mask layer which overlays a semiconductor layer. The semiconductor layer has areas of a first semiconductor material and a second semiconductor material in contact with the hard mask layer. The process includes applying a first conformal coating on the hard mask layer and the series of mandrels, to form spacer layer sacrificial fins. The process includes removing the first conformal coating from horizontal surfaces while retaining the first conformal coating on sidewalls of the series of mandrels. The process includes removing the series of mandrels and etching into a material of the hard mask layer using the spacer layer sacrificial fins as a mask.

公开(公告)号：US09704866B2

公开(公告)日：2017-07-11

申请号：US14997773

申请日：2016-01-18

Applicant: International Business Machines Corporation

Inventor： Effendi Leobandung

IPC: H01L27/12 ,  H01L21/84 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/775 ,  H01L29/78 ,  H01L21/8258 ,  H01L21/324 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/51

CPC classification number: H01L27/0924 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/517 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/7848

Abstract: In one aspect thereof the invention provides a structure that includes a substrate having a surface and a plurality of fins supported by the surface of the substrate. The plurality of fins are formed of Group IVA-based crystalline semiconductor material and are spaced apart and generally parallel to one another. In the structure at least some of the plurality of fins comprise an amorphous region forming a nanowire precursor structure that is located along a length of the fin where a Group III-V transistor is to be located. A method to fabricate the structure and other structures is also disclosed.

公开(公告)号：US09691865B2

公开(公告)日：2017-06-27

申请号：US15238857

申请日：2016-08-17

Applicant: Kabushiki Kaisha Toshiba

Inventor： Kazutaka Takagi

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/778 ,  H01L29/20 ,  H01L29/201 ,  H01L29/423

CPC classification number: H01L29/41758 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/812

Abstract: A high frequency semiconductor device includes a stacked body, a gate electrode, a source electrode and a drain electrode. The gate electrode includes a bending gate part and a straight gate part. The bending gate part is extended in a zigzag shape and has first and second outer edges. The source electrode includes a bending source part and a straight source part. The bending source part has an outer edge spaced by a first distance from the first outer edge of the bending gate part along a normal direction. The drain electrode includes a bending drain part and a straight drain part. The bending drain part has an outer edge spaced by a second distance from the second outer edge of the bending gate part along the normal direction.