公开(公告)号：US20240282827A1

公开(公告)日：2024-08-22

申请号：US18172916

申请日：2023-02-22

Applicant: GAN SYSTEMS INC.

Inventor： Marco A. ZUNIGA ,  Thomas William MACELWEE ,  Rohan SAMSI ,  Lucas Andrew Milner ,  Vineet Unni ,  Jayasimha S. PRASAD ,  Ashutosh Ravindra JOHARAPURKAR ,  Ramesh G. KARPUR

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/201 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/7786

Abstract: The biasing of one or more field plates of a high electron mobility transistor (a HEMT) with a non-zero voltage to thereby affect the electric field profile of the HEMT. The non-zero voltage may be a constant DC voltage, or perhaps may be a voltage that changes over time. The use of a non-zero voltage allows for greater ability to regulate and reduce the electric field occurring in the semiconductor channel region, especially at the field plate. Further, when the electric field occurring at the field plate is reduced, the overall size of the HEMT can also be reduced as compared to applying a zero voltage to the field plate. Alternatively, or in addition, applying a non-zero voltage to the field plate allows the voltage levels handled by the HEMT to be increased as compared to simply grounding the field plate.

公开(公告)号：US11935943B2

公开(公告)日：2024-03-19

申请号：US17571694

申请日：2022-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Kwan Yu ,  Seung Hun Lee ,  Yang Xu

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/20 ,  H01L29/201 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain.

公开(公告)号：US20230395707A1

公开(公告)日：2023-12-07

申请号：US18455136

申请日：2023-08-24

Applicant: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.

Inventor： Simon FICHTNER ,  Fabian LOFINK ,  Bernhard WAGNER ,  Holger KAPELS

IPC: H01L29/778 ,  H01L29/04 ,  H01L29/20 ,  H01L29/201 ,  H01L29/417

CPC classification number: H01L29/7786 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/41766

Abstract: An electronic component comprises a first layer and a second layer, wherein a main surface of the first layer is arranged opposite a main surface of the second layer. The first layer comprises a polarized first material. A polarization of the first material faces in a first direction. The second layer comprises a polarized second material having at least one polarization state, wherein a direction of a polarization of the second material at least in the one polarization state of the second material is at least in part opposite to the first direction such that a charge zone forms along the main surface of the first and/or the second layer, said charge zone being electrically conductive at least when the second material is in the one polarization state.

公开(公告)号：US20220140088A1

公开(公告)日：2022-05-05

申请号：US17579122

申请日：2022-01-19

Applicant: AZUR SPACE Solar Power GmbH ,  3-5 Power Electronics GmbH

Inventor： Daniel FUHRMANN ,  Gregor KELLER ,  Clemens WAECHTER ,  Volker DUDEK

IPC: H01L29/15 ,  H01L29/06 ,  H01L29/10 ,  H01L29/201 ,  H01L29/861

Abstract: A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.

公开(公告)号：US11322600B2

公开(公告)日：2022-05-03

申请号：US16601570

申请日：2019-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/201 ,  H01L29/40 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a first passivation layer adjacent to two sides of the gate electrode, and a p-type semiconductor layer between the gate electrode and the barrier layer. Preferably, a corner of the p-type semiconductor layer contacting a sidewall of the first passivation layer includes a first curve, and a bottom surface of the p-type semiconductor layer directly on the first passivation layer includes a second curve.

公开(公告)号：US11107905B2

公开(公告)日：2021-08-31

申请号：US16653589

申请日：2019-10-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xin Miao ,  Chen Zhang ,  Kangguo Cheng ,  Wenyu Xu

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/335 ,  H01L21/324 ,  H01L21/225 ,  H01L29/10 ,  H01L29/221 ,  H01L29/16 ,  H01L29/161 ,  H01L29/201 ,  H01L29/22

Abstract: A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.

公开(公告)号：US20210226047A1

公开(公告)日：2021-07-22

申请号：US17207067

申请日：2021-03-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： YAO-CHUNG CHANG ,  PO-CHIH CHEN ,  JIUN-LEI JERRY YU ,  CHUN LIN TSAI

IPC: H01L29/778 ,  H01L29/20 ,  H01L21/324 ,  H01L29/66 ,  H01L29/201

Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.

公开(公告)号：US11031315B2

公开(公告)日：2021-06-08

申请号：US16290464

申请日：2019-03-01

Applicant: Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

Inventor： Fei Zhou

IPC: H01L29/66 ,  H01L29/78 ,  H01L23/373 ,  H01L29/08 ,  H01L29/16 ,  H01L29/201 ,  H01L29/161

Abstract: A method for fabricating a semiconductor structure includes providing a substrate and forming a plurality of fins on a surface of the substrate. Along an extending direction of the fins, the fins include first regions, second regions, and gate structures across the second regions. The first regions are located at both sides of the second regions. The method also includes forming first openings in the fins by removing the first regions of the fins at both sides of the gate structures until the substrate is exposed. Further, the method includes forming thermal conductive layers in the first openings, and forming doped layers on top surfaces of the thermal conductive layers. A material of the fins has a first thermal conductivity, a material of the thermal conductive layers have a second thermal conductivity, and the second thermal conductivity is larger than the first thermal conductivity.

公开(公告)号：US10978583B2

公开(公告)日：2021-04-13

申请号：US16194760

申请日：2018-11-19

Applicant: Cree, Inc.

Inventor： Yueying Liu ,  Saptharishi Sriram ,  Scott Sheppard ,  Jennifer Gao

IPC: H01L29/76 ,  H01L29/201 ,  H01L29/10 ,  H01L29/47 ,  H01L29/778 ,  H01L29/423 ,  H01L29/417 ,  H03F3/193 ,  H03F3/21 ,  H01L27/085 ,  H01L29/06 ,  H03F3/42 ,  H03F3/195 ,  H03F1/32 ,  H01L29/20

Abstract: A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.

公开(公告)号：US20210083073A1

公开(公告)日：2021-03-18

申请号：US16601570

申请日：2019-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/201 ,  H01L29/40 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a first passivation layer adjacent to two sides of the gate electrode, and a p-type semiconductor layer between the gate electrode and the barrier layer. Preferably, a corner of the p-type semiconductor layer contacting a sidewall of the first passivation layer includes a first curve, and a bottom surface of the p-type semiconductor layer directly on the first passivation layer includes a second curve.