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    MULTI-ADDRESS SPACE COLLECTIVES ENGINE
    42.
    发明公开
    MULTI-ADDRESS SPACE COLLECTIVES ENGINE 审中-公开

    公开(公告)号：US20240202132A1

    公开(公告)日：2024-06-20

    申请号：US18478911

    申请日：2023-09-29

    Applicant: ATI Technologies ULC

    Inventor： Benjamin Wong ,  Philip Ng

    IPC: G06F12/10

    CPC classification number: G06F12/10

    Abstract: The disclosed device includes a collectives engine that can offload collectives communications of multiple nodes and perform collective operations. The collectives engine can manage a direct mapping scheme of local memories of the nodes for access by the collectives engine. Various other methods, systems, and computer-readable media are also disclosed.

    Benefit-based bitrate distribution for video encoding
    46.
    发明授权
    Benefit-based bitrate distribution for video encoding 有权

    公开(公告)号：US11997275B2

    公开(公告)日：2024-05-28

    申请号：US16113302

    申请日：2018-08-27

    Applicant: ATI TECHNOLOGIES ULC

    Inventor： Boris Ivanovic ,  Mehdi Saeedi

    IPC: H04N11/02 ,  H04N19/124 ,  H04N19/154

    CPC classification number: H04N19/124 ,  H04N19/154

    Abstract: A multimedia system allocates, during encoding of a multimedia stream, bits to portions of frames based on quality metrics and bit usages for different quantization parameters (QPs). An encoder of the multimedia system encodes a frame in a first pass with a first QP and in a second pass with a second QP. A comparator of the multimedia system measures and compares quality metrics, such as mean squared error, for each portion of the frame encoded with the first QP and the second QP. The comparator compares the difference between the quality metrics for each portion encoded with each QP to a threshold. If the difference in quality metrics for a portion exceeds the threshold, the comparator selects the portion for inclusion in a subset of portions to be encoded with the second QP.

    FLIPPED VOLTAGE FOLLOWER LOW-DROPOUT REGULATOR WITH FREQUENCY COMPENSATION
    48.
    发明公开
    FLIPPED VOLTAGE FOLLOWER LOW-DROPOUT REGULATOR WITH FREQUENCY COMPENSATION 审中-公开

    公开(公告)号：US20240143007A1

    公开(公告)日：2024-05-02

    申请号：US17977289

    申请日：2022-10-31

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Achal Kathuria ,  Tom Moiannou ,  Pradeep Jayaraman ,  Karthik Gopalakrishnan

    IPC: G05F1/575 ,  G05F1/565 ,  H03F3/45

    CPC classification number: G05F1/575 ,  G05F1/565 ,  H03F3/45192

    Abstract: A voltage regulator includes an input power supply node, an output regulated power supply node, a flipped voltage follower circuit, and a compensation capacitor. The flipped voltage follower circuit includes an output transistor configured as a common-source amplifier circuit. A source terminal of the output transistor is coupled to the input power supply node and a drain terminal of the output transistor is coupled to the output regulated power supply node. The flipped voltage follower circuit includes a folded cascode feedback circuit. The folded cascode feedback circuit includes a folding node. The folded cascode feedback circuit is configured to receive an output regulated voltage on the output regulated power supply node and to provide a feedback signal to a gate terminal of the output transistor. The compensation capacitor is coupled to the output regulated power supply node and the folding node.

    Adaptive DCO VF curve slope control
    49.
    发明授权
    Adaptive DCO VF curve slope control 有权

    公开(公告)号：US11962313B2

    公开(公告)日：2024-04-16

    申请号：US16370479

    申请日：2019-03-29

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Stephen Victor Kosonocky ,  Mikhail Rodionov ,  Joyce Cheuk Wai Wong

    IPC: H03L7/099 ,  H03K5/14 ,  H03K5/00

    CPC classification number: H03L7/0991 ,  H03K5/14 ,  H03K2005/00058

    Abstract: An oscillator circuit is provided that adapts to voltage supply variations. The circuit first and second delays lines connected inputs of an edge detector, one delay line supplied by a reference voltage and the other with a drooping supply voltage. The edge detector generates an output clock based on a relationship between the inputs. The output clock applied to the signal inputs of the first and second delay lines. The output clock has a voltage dependent frequency performance curve with a slope dependent at least on the second delay line delay and a delay of the edge detector. At least one of the first delay line, the second delay line, and the edge detector delay are adjusted to change the slope of the performance curve.

    Unified kernel virtual address space for heterogeneous computing
    50.
    发明授权
    Unified kernel virtual address space for heterogeneous computing 有权

    公开(公告)号：US11960410B2

    公开(公告)日：2024-04-16

    申请号：US17105331

    申请日：2020-11-25

    Applicant: ATI Technologies ULC

    Inventor： Tung Chuen Kwong ,  Benjamin Koon Pan Chan ,  William Lloyd Atkinson

    IPC: G06F12/1009 ,  G06F9/54 ,  G06F12/02

    CPC classification number: G06F12/1009 ,  G06F9/544 ,  G06F9/545 ,  G06F12/0246

    Abstract: Systems, apparatuses, and methods for implementing a unified kernel virtual address space for heterogeneous computing are disclosed. A system includes at least a first subsystem running a first kernel, an input/output memory management unit (IOMMU), and a second subsystem running a second kernel. In order to share a memory buffer between the two subsystems, the first subsystem allocates a block of memory in part of the system memory controlled by the first subsystem. A first mapping is created from a first logical address of the kernel address space of the first subsystem to the block of memory. Then, the IOMMU creates a second mapping to map the physical address of that block of memory from a second logical address of the kernel address space of the second subsystem. These mappings allow the first and second subsystems to share buffer pointers which reference the block of memory.

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