Patent search ap:"Chung-Lin Wu" Page 5

41.

发明授权
Mandrel assembly 失效
Title translation: 心轴组件

公开(公告)号：US5580416A

公开(公告)日：1996-12-03

申请号：US381038

申请日：1995-01-31

Applicant: Chin-I Lin , Chung-Lin Wu , Rong-Shian Liu , Gou-Don Chu

Inventor： Chin-I Lin , Chung-Lin Wu , Rong-Shian Liu , Gou-Don Chu

IPC: B29C70/16 , B29C33/48 , B29C53/82 , B29C70/06 , B29C70/32 , B29K105/08 , B29L22/00 , B65H81/00

CPC classification number: B29C70/32 , B29C53/821 , B29C53/824 , B29C33/48

Abstract: A mandrel assembly has a hollow main tube and two annular sleeves, wherein an inner diameter of the two annular sleeves is larger than an outer diameter of the two main tube ends. The two annular sleeves are sleeved respectively on the two main tube ends, which can be easily disengaged from the mandrel assembly when applied with an external force.

Abstract translation: 心轴组件具有中空主管和两个环形套筒，其中两个环形套筒的内径大于两个主管端部的外径。两个环形套筒分别套在两个主管端上，当外力施加时，它们可以容易地从心轴组件脱离。

42.

发明授权
Flash memory storage device, controller thereof, and data programming method thereof 有权
Title translation: 闪存存储装置及其控制器及其数据编程方法

公开(公告)号：US08706952B2

公开(公告)日：2014-04-22

申请号：US12766265

申请日：2010-04-23

Applicant: Chih-Jen Hsu , Yi-Hsiang Huang , Chung-Lin Wu

Inventor： Chih-Jen Hsu , Yi-Hsiang Huang , Chung-Lin Wu

IPC: G06F12/00 , G06F13/00 , G06F13/28 , G11C11/34 , G11C16/04 , G11C7/00

CPC classification number: G06F12/00 , G06F12/02 , G06F12/06

Abstract: A flash memory storage device, a controller thereof, and a data programming method are provided. The flash memory storage device has a flash memory comprising a plurality of physical blocks, each physical block includes a plurality of physical addresses, and the physical addresses comprises at least one fast physical address and at least one slow physical address. The method comprises at least grouping the physical blocks into a data area and a spare area; setting a predetermined block number; obtaining m physical blocks from the spare area, receiving a write command comprising a write data and a logical address, determining a logical address range of a buffer according to the logical address and the predetermined block number. When all logical addresses to be programmed with the write data are within the logical address range of the buffer, using a fast mode to program the data into the m physical blocks.

Abstract translation: 提供一种闪速存储器存储装置，其控制器和数据编程方法。闪速存储器存储设备具有包括多个物理块的闪存，每个物理块包括多个物理地址，并且物理地址包括至少一个快速物理地址和至少一个慢物理地址。该方法包括至少将物理块分组成数据区和备用区; 设定预定的块号; 从备用区获取m个物理块，接收包括写数据和逻辑地址的写命令，根据逻辑地址和预定块号确定缓冲器的逻辑地址范围。当要写入数据的所有逻辑地址都在缓冲区的逻辑地址范围内时，使用快速模式将数据编程到m个物理块中。

43.

发明授权
Vertical MOSFET transistor having source/drain contacts disposed on the same side and method for manufacturing the same 有权
Title translation: 具有设置在同一侧的源极/漏极触点的垂直MOSFET晶体管及其制造方法

公开(公告)号：US08487371B2

公开(公告)日：2013-07-16

申请号：US13074921

申请日：2011-03-29

Applicant: Daniel M. Kinzer , Steven Sapp , Chung-Lin Wu , Oseob Jeon , Bigildis Dosdos

Inventor： Daniel M. Kinzer , Steven Sapp , Chung-Lin Wu , Oseob Jeon , Bigildis Dosdos

IPC: H01L29/66 , H01L23/62 , H01L27/088 , H01L21/338

CPC classification number: H01L29/7827 , H01L24/13 , H01L29/41766 , H01L29/66666 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L2224/131 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/00

Abstract: Systems and methods of fabricating Wafer Level Chip Scale Packaging (WLCSP) devices with transistors having source, drain and gate contacts on one side of the transistor while still having excellent electrical performance with low drain-to-source resistance RDS(on) include using a two-metal drain contact technique. The RDS(on) is further improved by using a through-silicon-via (TSV) technique to form a drain contact or by using a copper layer closely connected to the drain drift.

Abstract translation: 具有晶体管的晶体管的晶体管的晶体管的一侧制造晶圆级芯片级封装（WLCSP）器件的系统和方法仍然具有优异的电气性能，低漏极 - 源极电阻RDS（on）包括使用双金属漏极接触技术。通过使用穿硅通孔（TSV）技术来形成漏极接触或通过使用紧密连接到漏极漂移的铜层来进一步改善RDS（on）。

44.

发明授权
Block management method for flash memory, and flash memory controller and flash memory storage device using the same 有权
Title translation: 闪存的块管理方法，闪存控制器和闪存存储设备使用相同

公开(公告)号：US08230162B2

公开(公告)日：2012-07-24

申请号：US12705325

申请日：2010-02-12

Applicant: Hsiang-Hsiung Yu , Yi-Hsiang Huang , Chung-Lin Wu , Yu-Chung Shen

Inventor： Hsiang-Hsiung Yu , Yi-Hsiang Huang , Chung-Lin Wu , Yu-Chung Shen

IPC: G06F12/14

CPC classification number: G06F21/6209

Abstract: A block management method for managing blocks of a flash memory storage device is provided. The flash memory storage device includes a flash memory controller. The block management method includes the following steps. At least a part of the blocks is grouped into a first partition and a second partition. Whether an authentication code exists is determined. When the authentication code exists, the blocks belonging to the first partition are provided for a host system to access, so the host system displays the first partition and hides the second partition. An authentication information is received from the host system. Whether the authentication information and the authentication code are identical is authenticated. When the authentication information and the authentication code are identical, the blocks belonging to the second partition are provided for the host system to access, so the host system displays the second partition and hides the first partition.

Abstract translation: 提供一种用于管理闪存存储设备的块的块管理方法。闪存存储设备包括闪存控制器。块管理方法包括以下步骤。至少一部分块被分组成第一分区和第二分区。确定是否存在认证码。当认证码存在时，属于第一分区的块被提供给主机系统进行访问，因此主机系统显示第一个分区并隐藏第二个分区。从主机系统接收认证信息。认证信息和验证码是否相同是否通过认证。当认证信息和认证码相同时，属于第二分区的块被提供给主机系统访问，所以主机系统显示第二分区并隐藏第一分区。

45.

发明授权
Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same 失效
Title translation: 用于晶圆级芯片尺寸封装的半导体晶片结构，用于使用它们的功率器件，封装和系统及其制造方法

公开(公告)号：US08058732B2

公开(公告)日：2011-11-15

申请号：US12275086

申请日：2008-11-20

Applicant: Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit

Inventor： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit

IPC: H01L23/48

CPC classification number: H01L29/7802 , H01L23/3114 , H01L23/36 , H01L23/482 , H01L24/16 , H01L24/19 , H01L24/31 , H01L29/0657 , H01L2224/04105 , H01L2224/20 , H01L2224/73253 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/351 , H01L2924/00

Abstract: Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.

Abstract translation: 公开了半导体管芯结构，其使具有垂直功率器件的管芯封装在晶片级芯片级封装中，其中导电端子存在于管芯的一个表面处，并且器件具有非常低的导通状态抵抗性。在示例性实施例中，沟槽和孔形成在管芯的背面，孔与导管的顶表面处的导电区接触。可以在沟槽和孔上设置导电层和/或导体，以将器件的背面导电电极电耦合到导电区域。还公开了使用根据本发明的具有模具结构的模具的封装和系统，以及根据本发明的具有模具结构的模具的方法。

46.

发明申请
THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS PACKAGE 失效
Title translation: 热增强型和双重散热模具无铅包装

公开(公告)号：US20110124158A1

公开(公告)日：2011-05-26

申请号：US13019488

申请日：2011-02-02

Applicant: Chung-Lin Wu , Rajeev D. Joshi

Inventor： Chung-Lin Wu , Rajeev D. Joshi

IPC: H01L21/56

CPC classification number: H01L21/561 , H01L21/4828 , H01L23/4334 , H01L23/49548 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2221/68377 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49113 , H01L2224/73265 , H01L2224/83 , H01L2224/85 , H01L2224/92247 , H01L2224/97 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012

Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.

Abstract translation: 半导体封装包括半导体器件30和模制的上部散热器10.散热器具有面向半导体器件的内表面16和至少部分地暴露于封装器件周围环境的外表面15。环形平面基座11围绕凸出或突出的中心区域12.该区域由基座11的平面支承在四个倾斜壁13.1-13.4之上。壁相对于平面环形基座呈锐角倾斜，并朝向上散热片10的中心倾斜。环形基座11的外周围是四个支撑臂18.1-18.4。支撑臂相对于平面环形基座11的内表面16以钝角设置。

47.

发明申请
SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME 有权
Title translation: 半导体封装及其制造方法

公开(公告)号：US20100258925A1

公开(公告)日：2010-10-14

申请号：US12823411

申请日：2010-06-25

Applicant: Oseob Jeon , Yoonhwa Choi , Boon Huan Gooi , Maria Cristina B. Estacio , David Chong , Tan Teik Keng , Shibaek Nam , Rajeev Joshi , Chung-Lin Wu , Venkat Iyer , Lay Yeap Lim , Byoung-Ok Lee

Inventor： Oseob Jeon , Yoonhwa Choi , Boon Huan Gooi , Maria Cristina B. Estacio , David Chong , Tan Teik Keng , Shibaek Nam , Rajeev Joshi , Chung-Lin Wu , Venkat Iyer , Lay Yeap Lim , Byoung-Ok Lee

IPC: H01L23/28 , H01L21/56

CPC classification number: H01L24/29 , H01L21/561 , H01L23/3121 , H01L23/4951 , H01L23/49558 , H01L23/49562 , H01L23/49575 , H01L23/49861 , H01L24/32 , H01L24/36 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/97 , H01L25/0655 , H01L2223/54406 , H01L2223/54486 , H01L2224/16 , H01L2224/291 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/293 , H01L2224/32057 , H01L2224/32225 , H01L2224/40245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45169 , H01L2224/45565 , H01L2224/456 , H01L2224/45644 , H01L2224/45669 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48237 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49113 , H01L2224/4943 , H01L2224/73204 , H01L2224/73265 , H01L2224/83192 , H01L2224/83385 , H01L2224/83801 , H01L2224/8385 , H01L2224/85013 , H01L2224/97 , H01L2924/00013 , H01L2924/00014 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/1815 , H01L2924/19043 , H01L2924/30107 , H01L2224/85 , H01L2924/00 , H01L2924/0105 , H01L2924/01082 , H01L2924/00012 , H01L2224/13111 , H01L2924/0665 , H01L2224/29099 , H01L2224/29199 , H01L2224/37099

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract translation: 公开了半导体管芯封装。示例性半导体管芯封装包括预成型衬底。预成型基板可以具有附接到其上的半导体管芯，并且封装材料可以设置在半导体管芯上方。

48.

发明申请
SEMICONDUCTOR PACKAGE WITH LEAD INTRUSIONS 审中-公开
Title translation: 半导体封装与引线插入

公开(公告)号：US20090261461A1

公开(公告)日：2009-10-22

申请号：US12104182

申请日：2008-04-16

Applicant: Steven Sapp , Chung-Lin Wu , Maria Christina B. Estacio , Bigildis Dosdos , Hamza Yilmaz

Inventor： Steven Sapp , Chung-Lin Wu , Maria Christina B. Estacio , Bigildis Dosdos , Hamza Yilmaz

IPC: H01L23/495 , H01L21/60

CPC classification number: H01L23/49562 , H01L23/49524 , H01L23/49548 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/37147 , H01L2224/45014 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48095 , H01L2224/4813 , H01L2224/48247 , H01L2224/4846 , H01L2224/48472 , H01L2224/48599 , H01L2224/48699 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/73265 , H01L2224/84801 , H01L2224/8485 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599 , H01L2924/206

Abstract: Semiconductor packages comprising a plurality of lead fingers containing a lead intrusion at the edge of the lead fingers are described. The semiconductor packages comprise an integrated circuit chip that is connected to a die pad and is electrically connected to multiple lead fingers. One or more of the lead fingers may have a lead intrusion disposed on the external exposed lower surface of the lead finger. The lead intrusion may have a height that is about ⅕ to about ½ the height of a lead finger, a width that is about ⅕ to about 1/2 the width of a lead finger, and a depth that is about ¼ to about ¾ the length of the externally exposed lower surface of a lead finger. The lead intrusion increases the area on the lead finger that contacts a bond material, such as solder, and therefore increase the strength of the joint between the semiconductor package and an external surface to which the lead finger is connected (i.e., a PCB). The lead intrusion allows out gassing during reflow of the bond material which may reduce voiding. The lead intrusion can also increase bond joint reliability by providing longer crack propagation length.

Abstract translation: 描述了包括在引线的边缘处包含铅侵入的多个引线指的半导体封装。半导体封装包括连接到管芯焊盘并且电连接到多个引线指的集成电路芯片。一个或多个引导指可以具有设置在引线指的外部暴露下表面上的引线侵入。引线入侵可以具有引导指的高度的约1/5至约1/2的高度，宽度是引线指的宽度的大约1/5至大约1/2，并且深度约为1/4 到铅笔的外部暴露的下表面的长度的约3/4。引线入侵增加了引线接触诸如焊料的接合材料的引线区域，因此增加了半导体封装与引线指连接的外表面（即PCB）之间的接合强度。铅侵入允许在回流焊接材料期间放气，这可能减少空隙。铅侵入也可以通过提供更长的裂纹扩展长度来增加接合点的可靠性。

49.

发明申请
Device and method for optical nanoindentation measurement 有权
Title translation: 光学纳米压痕测量的装置和方法

公开(公告)号：US20090165537A1

公开(公告)日：2009-07-02

申请号：US12230340

申请日：2008-08-28

Applicant: Jiong-Shiun Hsu , Hui-Ching Lu , Chung-Lin Wu , Sheng-Jui Chen

Inventor： Jiong-Shiun Hsu , Hui-Ching Lu , Chung-Lin Wu , Sheng-Jui Chen

IPC: G01N3/48

CPC classification number: G01N3/405 , G01N2203/0286 , G01N2203/0641 , G01Q60/366

Abstract: This invention relates to a device and method for optical nanoindentation measurement, according to which respective measurement results are obtained by having an indenter tip apply load to a fixed portion of a thin film, having an indenter tip apply load to a non-fixed portion of a thin film, and having a vibrating component transmit the dynamic properties of the vibration to the thin film. By combining the above measurement results in calculations, the Young's modulus, the Poisson's ratio, and the density of the thin film can be obtained.

Abstract translation: 本发明涉及一种用于光学纳米压痕测量的装置和方法，根据该装置和方法，通过将压头施加载荷施加到薄膜的固定部分上，获得各自的测量结果，该固定部分具有压头施加载荷到非固定部分并且具有振动分量的薄膜将振动的动态特性传递给薄膜。通过在计算中结合上述测量结果，可以获得杨氏模量，泊松比和薄膜的密度。