公开(公告)号：US20120264296A1

公开(公告)日：2012-10-18

申请号：US13086542

申请日：2011-04-14

Applicant: Chyi Shyuan CHERN ,  Hsin-Hsien WU ,  Chun-Lin CHANG ,  Hsing-Kuo HSIA ,  Hung-Yi KUO

Inventor： Chyi Shyuan CHERN ,  Hsin-Hsien WU ,  Chun-Lin CHANG ,  Hsing-Kuo HSIA ,  Hung-Yi KUO

IPC: H01L21/768

CPC classification number: H01L21/76801 ,  H01L21/02057 ,  H01L21/3065 ,  H01L21/76898

Abstract: A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical.

Abstract translation: 形成贯通硅通孔（TSV）开口的方法包括通过基板形成TSV开口。 使用第一种化学物质去除在TSV开口的侧壁上的衬底的材料的重铸。 TSV开口的侧壁通过基本上除去第一种化学物质的残留物而用第二种化学品清洗。

公开(公告)号：US20120244652A1

公开(公告)日：2012-09-27

申请号：US13053701

申请日：2011-03-22

Applicant: Yung-Chang CHEN ,  Hsin-Hsien WU ,  Chyi Shyuan CHERN ,  Ching-Wen HSIAO ,  Fu-Wen LIU ,  Kuang-Huan HSU

Inventor： Yung-Chang CHEN ,  Hsin-Hsien WU ,  Chyi Shyuan CHERN ,  Ching-Wen HSIAO ,  Fu-Wen LIU ,  Kuang-Huan HSU

IPC: H01L33/58

CPC classification number: H01L33/505 ,  H01L25/167 ,  H01L33/486 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2933/0041 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An embodiment of the disclosure includes a method of fabricating a plurality of light emitting diode devices. A plurality of LED dies is provided. The LED dies are bonded to a carrier substrate. A patterned mask layer comprising a plurality of openings is formed on the carrier substrate. Each one of the plurality of LED dies is exposed through one of the plurality of the openings respectively. Each of the plurality of openings is filled with a phosphor. The phosphor is cured. The phosphor and the patterned mask layer are polished to thin the phosphor covering each of the plurality of LED dies. The patterned mask layer is removed after polishing the phosphor.

Abstract translation: 本公开的实施例包括制造多个发光二极管器件的方法。 提供多个LED管芯。 LED管芯结合到载体衬底。 包含多个开口的图案化掩模层形成在载体衬底上。 多个LED管芯中的每一个分别通过多个开口中的一个露出。 多个开口中的每一个都填充有荧光体。 磷光体被固化。 对磷光体和图案化掩模层进行抛光以使覆盖多个LED管芯中的每一个的磷光体变薄。 在抛光荧光体之后去除图案化的掩模层。

公开(公告)号：US08241924B2

公开(公告)日：2012-08-14

申请号：US12394201

申请日：2009-02-27

Applicant: Nai-Han Cheng ,  Chyi Shyuan Chern

Inventor： Nai-Han Cheng ,  Chyi Shyuan Chern

IPC: H01L21/66 ,  G01R31/26

CPC classification number: H01L21/26513 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for implant uniformity is provided that includes determining a variation of critical dimensions (CD) of a semiconductor wafer, moving the semiconductor wafer in a two-dimensional mode during an implantation process, and controlling a velocity of the movement of the semiconductor wafer so that an implant dose to the semiconductor wafer is varied based on the variation of CD.

Abstract translation: 提供了一种用于植入均匀性的方法，其包括确定半导体晶片的临界尺寸（CD）的变化，在注入过程期间以二维模式移动半导体晶片，以及控制半导体晶片的移动速度 基于CD的变化改变对半导体晶片的植入剂量的变化。

公开(公告)号：US20110086504A1

公开(公告)日：2011-04-14

申请号：US12879371

申请日：2010-09-10

Applicant: Kuo Bin HUANG ,  Hsin-Chien LU ,  Ryan Chia-Jen CHEN ,  Chi-Ming YANG ,  Chyi Shyuan CHERN ,  Chin-Hsiang LIN

Inventor： Kuo Bin HUANG ,  Hsin-Chien LU ,  Ryan Chia-Jen CHEN ,  Chi-Ming YANG ,  Chyi Shyuan CHERN ,  Chin-Hsiang LIN

IPC: H01L21/3205 ,  H01L21/302

CPC classification number: H01L21/28238 ,  H01L21/02071 ,  H01L21/823842 ,  H01L21/823857

Abstract: A method for forming an integrated circuit is provided. The method includes forming a gate dielectric structure over a substrate. A titanium-containing sacrificial layer is formed, contacting the gate dielectric structure. The whole titanium-containing sacrificial layer is substantially removed.

Abstract translation: 提供一种用于形成集成电路的方法。 该方法包括在衬底上形成栅极电介质结构。 形成与该栅电介质结构接触的含钛牺牲层。 基本上除去了整个含钛牺牲层。

公开(公告)号：US20100210041A1

公开(公告)日：2010-08-19

申请号：US12370746

申请日：2009-02-13

Applicant: Chun-Lin Chang ,  Hsin-Hsien Wu ,  Zin-Chang Wei ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Jun-Lin Yeh ,  Jih-Jse Lin ,  Jo-Fei Wang ,  Ming-Yu Fan ,  Jong-I Mou

Inventor： Chun-Lin Chang ,  Hsin-Hsien Wu ,  Zin-Chang Wei ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Jun-Lin Yeh ,  Jih-Jse Lin ,  Jo-Fei Wang ,  Ming-Yu Fan ,  Jong-I Mou

IPC: H01L21/66 ,  H01L21/306 ,  H01L21/26 ,  H01L21/265

CPC classification number: H01L22/20 ,  H01L21/67248 ,  H01L21/67253 ,  H01L22/12

Abstract: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.

Abstract translation: 一种装置包括被配置为执行离子注入工艺的处理室。 在处理室内设有冷却台板或静电吸盘。 冷却台板或静电卡盘构造成支撑半导体晶片。 冷却台板或静电卡盘具有多个温度区域。 每个温度区域包括在冷却压板或静电卡盘内或附近的至少一个流体导管。 提供至少两个冷却剂源，每个冷却剂源流体耦合到相应的一个流体管道，并且构造成在离子注入过程期间将分别不同的冷却剂供应到多个温度区中的相应的一个温度区。 冷却剂源分别包括不同的冷却或制冷装置。

公开(公告)号：US20100178772A1

公开(公告)日：2010-07-15

申请号：US12354394

申请日：2009-01-15

Applicant: Simon Su-Horng Lin ,  Yu-Ming Lee ,  Shao-Yen Ku ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Chin-Hsiang Lin

Inventor： Simon Su-Horng Lin ,  Yu-Ming Lee ,  Shao-Yen Ku ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Chin-Hsiang Lin

IPC: H01L21/306

CPC classification number: H01L21/31111 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/517

Abstract: The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [F—] concentration greater than 0.01 M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than −1.4 volts.

Abstract translation: 本公开提供了一种用于制造半导体器件的方法。 该方法包括提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，通过原位沉积工艺形成第一金属层和第一硅层，图案化第一硅 以去除覆盖在第二区域上的部分，使用图案化的第一硅层作为掩模来图案化第一金属层，以及去除图案化的第一硅层，包括施加溶液。 该溶液包括具有大于0.01M的[F-]浓度的第一组分，被配置为将溶液的pH调节至约4.3至约6.7的第二组分，以及将溶液的电位调节为 大于-1.4伏。

公开(公告)号：US20100167506A1

公开(公告)日：2010-07-01

申请号：US12347483

申请日：2008-12-31

Applicant: Simon Su-Horng LIN ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

Inventor： Simon Su-Horng LIN ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC: H01L21/30

CPC classification number: H01L21/3115 ,  H01J37/321 ,  H01J37/32706 ,  H01L21/2236 ,  H01L29/66795

Abstract: In some embodiments, a method of doping a semiconductor wafer disposed on a pedestal electrode in an inductive plasma chamber includes generating a plasma having a first voltage with respect to ground in the inductive plasma chamber, and applying a radio frequency (RF) voltage with respect to ground to the pedestal electrode in the inductive plasma chamber. The positive RF voltage is based on the first voltage of the plasma.

Abstract translation: 在一些实施例中，掺杂设置在感应等离子体室中的基座电极上的半导体晶片的方法包括在感应等离子体室中产生相对于接地的第一电压的等离子体，并且施加射频（RF）电压 接地到电感等离子体室中的基座电极。 正RF电压基于等离子体的第一电压。

公开(公告)号：US20100112912A1

公开(公告)日：2010-05-06

申请号：US12683033

申请日：2010-01-06

Applicant: Soon Kang Huang ,  Chih-Lung Lin ,  Chyi-Shyuan Chern

Inventor： Soon Kang Huang ,  Chih-Lung Lin ,  Chyi-Shyuan Chern

IPC: B24B57/02 ,  B24B7/20

CPC classification number: B24B37/32

Abstract: A retainer ring and a method of using the retainer ring are provided. The retainer ring has openings along a bottom surface. Grooves encompass the openings and extend to an interior portion of the retainer ring wherein a semiconductor wafer may be held. In operation, a semiconductor wafer is placed inside the retainer ring. As the retainer ring and the semiconductor wafer are moved relative to an underlying polishing pad, slurry is dispensed through the openings in the retainer ring. The grooves in the retainer ring allow the slurry to flow from the openings to the interior portion of the retainer ring and the semiconductor wafer.

Abstract translation: 提供了保持环和使用保持环的方法。 保持环具有沿底面的开口。 沟槽包围开口并延伸到保持环的内部，其中可以保持半导体晶片。 在操作中，将半导体晶片放置在保持环内。 当保持环和半导体晶片相对于下面的抛光垫移动时，通过保持环中的开口分配浆料。 保持环中的槽允许浆料从开口流到保持环和半导体晶片的内部。

公开(公告)号：US20080293339A1

公开(公告)日：2008-11-27

申请号：US11751468

申请日：2007-05-21

Applicant: Soon Kang Huang ,  Chih-Lung Lin ,  Chyi-Shyuan Chern

Inventor： Soon Kang Huang ,  Chih-Lung Lin ,  Chyi-Shyuan Chern

IPC: B24B5/00

CPC classification number: B24B37/32

Abstract: A retainer ring and a method of using the retainer ring are provided. The retainer ring has openings along a bottom surface. Grooves encompass the openings and extend to an interior portion of the retainer ring wherein a semiconductor wafer may be held. In operation, a semiconductor wafer is placed inside the retainer ring. As the retainer ring and the semiconductor wafer are moved relative to an underlying polishing pad, slurry is dispensed through the openings in the retainer ring. The grooves in the retainer ring allow the slurry to flow from the openings to the interior portion of the retainer ring and the semiconductor wafer.

Abstract translation: 提供了保持环和使用保持环的方法。 保持环具有沿底面的开口。 沟槽包围开口并延伸到保持环的内部，其中可以保持半导体晶片。 在操作中，将半导体晶片放置在保持环内。 当保持环和半导体晶片相对于下面的抛光垫移动时，通过保持环中的开口分配浆料。 保持环中的槽允许浆料从开口流到保持环和半导体晶片的内部。

公开(公告)号：US07195537B1

公开(公告)日：2007-03-27

申请号：US11245532

申请日：2005-10-07

Applicant: Volume Chien ,  Chyi-Shyuan Chern ,  Yu Yuan Kuo ,  Ming-Te Mo

Inventor： Volume Chien ,  Chyi-Shyuan Chern ,  Yu Yuan Kuo ,  Ming-Te Mo

IPC: B24B49/00

CPC classification number: B24B37/04 ,  B24B51/00

Abstract: A system of process control is provided. The system comprises a first processing tool, a first sensor, a second processing tool, and a processor. The first processing tool processes a first workpiece. The first sensor provides real-time monitoring (RTM) data of the first processing tool while processing the first workpiece. The second processing tool processes the first workpiece subsequent to the first processing tool. The processor adjusts, according to the real-time monitoring data and a preset program, the first processing tool for processing a second workpiece, and the second processing tool for processing the first workpiece.

Abstract translation: 提供了一种过程控制系统。 该系统包括第一处理工具，第一传感器，第二处理工具和处理器。 第一加工工具处理第一工件。 第一个传感器在处理第一个工件时提供第一个处理工具的实时监控（RTM）数据。 第二处理工具在第一处理工具之后处理第一工件。 处理器根据实时监视数据和预设程序调整用于处理第二工件的第一处理工具和用于处理第一工件的第二处理工具。