公开(公告)号：US08806898B2

公开(公告)日：2014-08-19

申请号：US13022461

申请日：2011-02-07

Applicant: Jin Han ,  Sang-Oeb Na ,  Yang-Han Kim ,  Woo-Hyun Kim ,  Heui-Joon Park

Inventor： Jin Han ,  Sang-Oeb Na ,  Yang-Han Kim ,  Woo-Hyun Kim ,  Heui-Joon Park

IPC: C03B18/02 ,  C03B18/14 ,  C03C15/00

CPC classification number: C03B35/14 ,  B65G49/064 ,  B65G49/068 ,  C03B33/0235

Abstract: An layout for a glass manufacturing system may include a hot process part having a batch plant for storing a glass raw material, a tank for melting the raw material and storing a molten glass, a float bath for forming the molten glass into a glass of a ribbon shape, an annealing lehr for cooling the glass ribbon, and a cold end connected to the annealing lehr, and an etching process part having a final cutting sector for cutting the glass provided from the cold end into sheet glasses of a preset final size, a beveling and etching sector for bevel the edges of the cut sheet glasses and etching the beveled sheet glasses, and a first inspection sector for inspecting the etched sheet glasses, and the hot process part and the etching process part may be connected by a single conveyor to form a continuous line.

Abstract translation: 玻璃制造系统的布局可以包括具有用于存储玻璃原料的批量设备的热处理部件，用于熔化原料并储存熔融玻璃的罐，用于将熔融玻璃形成为玻璃的玻璃 丝带形状，用于冷却玻璃带的退火退火炉和连接到退火炉的冷端;以及蚀刻处理部件，其具有用于将从冷端提供的玻璃切割成预定最终尺寸的玻璃板的最终切割扇区， 斜切和蚀刻扇区，用于使切片片玻璃的边缘倾斜并蚀刻斜面片玻璃，以及用于检查蚀刻的片状玻璃的第一检查部分，热处理部分和蚀刻处理部分可以通过单个传送器 形成连续线。

公开(公告)号：US08803051B2

公开(公告)日：2014-08-12

申请号：US12935804

申请日：2009-04-01

Applicant: Sang-Ryul Lee ,  Kyu-Young Kim ,  Jae-Myung Chin ,  Dong-Han Kim ,  Si-Young Choi ,  Sung-Ho Choi

Inventor： Sang-Ryul Lee ,  Kyu-Young Kim ,  Jae-Myung Chin ,  Dong-Han Kim ,  Si-Young Choi ,  Sung-Ho Choi

IPC: H05B6/64 ,  H05B6/70

CPC classification number: H05B6/708

Abstract: A microwave oven includes a cavity having a cooking chamber; a magnetron oscillating microwave radiation used for cooking food in the cooking chamber; and a plurality of radiation openings through which the microwave radiation is radiated into the cooking chamber, each of the radiation openings having a length in a direction where the microwave radiation is guided by a waveguide, the length being greater or less than λ/4.

Abstract translation: 微波炉包括具有烹饪室的空腔; 用于在烹饪室中烹饪食物的磁控管振荡微波辐射; 以及多个辐射开口，微波辐射通过该辐射开口辐射到烹饪室中，每个辐射开口具有在微波辐射被波导引导的方向上的长度，该长度大于或小于λ/ 4。

公开(公告)号：US08787469B2

公开(公告)日：2014-07-22

申请号：US11972397

申请日：2008-01-10

Applicant: Sung Jin Kim ,  Bruno Clerckx ,  Seung Young Park ,  David J. Love ,  Il Han Kim

Inventor： Sung Jin Kim ,  Bruno Clerckx ,  Seung Young Park ,  David J. Love ,  Il Han Kim

IPC: H04K1/10 ,  H04L27/28

CPC classification number: H04B7/0417 ,  H04B7/0619 ,  H04L5/0023 ,  H04L5/0025 ,  H04L25/03343 ,  H04L2025/03426

Abstract: A base station includes a storage unit to store a codebook, wherein the codebook includes a plurality of matrices; a control unit to perform beamforming using the codebook to generate a signal; and a multi-antenna to transmit the signal. For all of the plurality of matrices, all column vectors of a same matrix of the plurality of matrices are orthogonal to each other. For all columns of the plurality of matrices, all column vectors of a same column of all of the plurality of matrices satisfy a Grassmannian line packing (GLP) criterion.

Abstract translation: 基站包括用于存储码本的存储单元，其中码本包括多个矩阵; 控制单元，用于使用码本来执行波束形成以产生信号; 以及用于发送信号的多天线。 对于所有多个矩阵，多个矩阵中相同矩阵的所有列向量彼此正交。 对于多个矩阵的所有列，所有多个矩阵的所有列的所有列向量满足Grassmannian线填充（GLP）标准。

公开(公告)号：US08773922B2

公开(公告)日：2014-07-08

申请号：US12614545

申请日：2009-11-09

Applicant: Seung-Hwan Song ,  Jaehong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Jun Jin Kong ,  Jong Han Kim

Inventor： Seung-Hwan Song ,  Jaehong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Jun Jin Kong ,  Jong Han Kim

IPC: G11C7/06

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C29/00 ,  G11C2211/5634

Abstract: A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit.

Abstract translation: 公开了一种非易失性半导体存储器件及确定读取电压的相关方法。 非易失性半导体存储器件包括： 包括多个存储单元的存储单元阵列，读电压确定单元，被配置为通过将在编程操作期间获得的参考数据与在随后的读取操作期间获得的比较数据进行比较来确定最佳读取电压，并将当前读取电压改变为新的 基于比较结果的读取电压和读取电压生成单元，被配置为响应于由读取电压确定单元提供的读取电压控制信号而产生新的读取电压。

公开(公告)号：US08737037B2

公开(公告)日：2014-05-27

申请号：US13333220

申请日：2011-12-21

Applicant: Jong Han Kim ,  Hyun Chul Jeong

Inventor： Jong Han Kim ,  Hyun Chul Jeong

IPC: H01G4/228

CPC classification number: H01G4/30 ,  H01C7/1006 ,  H01C7/13 ,  H01C7/18 ,  H01G4/0085 ,  H01G4/12

Abstract: There are provided a ceramic electronic component and a method of manufacturing the same. The ceramic electronic component includes: a ceramic element; and an internal electrode layer formed within the ceramic element, having a thickness of 0.5 μm or less, and including a non-electrode region formed therein, wherein an area ratio of the non-electrode region to an electrode region of the internal electrode layer, in a cross section of the internal electrode layer is between 0.1% and 10%, and the non-electrode region includes a ceramic component.

Abstract translation: 提供陶瓷电子部件及其制造方法。 陶瓷电子部件包括：陶瓷元件; 以及形成在所述陶瓷元件内的内部电极层，其厚度为0.5μm以下，并且包括形成在其中的非电极区域，其中所述非电极区域与所述内部电极层的电极区域的面积比， 内部电极层的截面积为0.1％〜10％，非电极区域为陶瓷成分。

公开(公告)号：US08699234B2

公开(公告)日：2014-04-15

申请号：US12984935

申请日：2011-01-05

Applicant: Han Kim ,  Mi-Ja Han ,  Dae-Hyun Park ,  Hyo-Jic Jung ,  Kang-Wook Bong

Inventor： Han Kim ,  Mi-Ja Han ,  Dae-Hyun Park ,  Hyo-Jic Jung ,  Kang-Wook Bong

IPC: H05K1/18

CPC classification number: H05K1/0236 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/15313 ,  H01L2924/16251 ,  H01L2924/3025 ,  H05K3/4694

Abstract: An EMI noise shield board, in which an EBG structure is inserted, includes a first board portion and a second board portion. The first board portion has an upper surface, on which an electronic part is disposed, and a circuit for transferring a signal and power to the electronic part. The second board portion is located on a lower surface of the first board portion. The electromagnetic bandgap structure is inserted into the second board portion, and has a band stop frequency property such that an EMI noise transferred from the first board portion is shielded from being radiated to the outside of the EMI noise shield board.

Abstract translation: 其中插入有EBG结构的EMI噪声屏蔽板包括第一板部分和第二板部分。 第一板部分具有设置有电子部件的上表面和用于将信号和电力传送到电子部件的电路。 第二板部分位于第一板部分的下表面上。 电磁带隙结构被插入到第二板部分中，并且具有阻挡频率特性，使得从第一板部分传送的EMI噪声被屏蔽而不被辐射到EMI噪声屏蔽板的外部。

公开(公告)号：US08678788B2

公开(公告)日：2014-03-25

申请号：US12739172

申请日：2008-10-10

Applicant: Jung-Hae Kim ,  Yoon-Seok Yang ,  Jaesang Park ,  Seong-Joon Hong ,  Dong-Han Kim ,  Seong-Yeol Hyeon

Inventor： Jung-Hae Kim ,  Yoon-Seok Yang ,  Jaesang Park ,  Seong-Joon Hong ,  Dong-Han Kim ,  Seong-Yeol Hyeon

IPC: F04B17/04

CPC classification number: F04B35/045 ,  F04B39/0044 ,  F04B39/121 ,  F04B39/122 ,  F04B39/127 ,  F04B39/14

Abstract: A linear compressor is provided. Unnecessary parts of a motor cover of the compressor are bent toward a rear cover in an axis direction to form supporting ends of the motor cover, and the supporting ends of the motor cover are welded directly to the rear cover, thereby considerably cutting down the material cost.

Abstract translation: 提供线性压缩机。 压缩机的电动机罩的不必要部分沿轴向朝向后盖弯曲，形成电动机罩的支承端，电动机盖的支承端直接焊接在后盖上，从而大大地减少材料 成本。

公开(公告)号：US20140042600A1

公开(公告)日：2014-02-13

申请号：US13962735

申请日：2013-08-08

Applicant: Jin Young Kim ,  No Sun Park ,  Yoon Joo Kim ,  Choon Heung Lee ,  Jin Han Kim ,  Seung Jae Lee ,  Se Woong Cha ,  Sung Kyu Kim ,  Glenn Rinne

Inventor： Jin Young Kim ,  No Sun Park ,  Yoon Joo Kim ,  Choon Heung Lee ,  Jin Han Kim ,  Seung Jae Lee ,  Se Woong Cha ,  Sung Kyu Kim ,  Glenn Rinne

IPC: H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/00 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3171 ,  H01L24/09 ,  H01L24/19 ,  H01L24/73 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2924/1461 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/00

Abstract: A semiconductor package and manufacturing method thereof are disclosed and may include a first semiconductor device comprising a first bond pad on a first surface of the first semiconductor device, a first encapsulant material surrounding side edges of the first semiconductor device, and a redistribution layer (RDL) formed on the first surface of the first semiconductor device and on a first surface of the encapsulant material. The RDL may electrically couple the first bond pad to a second bond pad formed above the first surface of the encapsulant material. A second semiconductor device comprising a third bond pad on a first surface of the second semiconductor device may face the first surface of the first semiconductor device and be electrically coupled to the first bond pad on the first semiconductor device. The first surface of the first semiconductor device may be coplanar with the first surface of the encapsulant material.

Abstract translation: 公开了半导体封装及其制造方法，并且可以包括第一半导体器件，其包括在第一半导体器件的第一表面上的第一接合焊盘，围绕第一半导体器件的侧边缘的第一密封材料和再分配层（RDL ）形成在第一半导体器件的第一表面上并且在密封剂材料的第一表面上。 RDL可以将第一接合焊盘电耦合到形成在密封剂材料的第一表面上方的第二接合焊盘。 包括在第二半导体器件的第一表面上的第三接合焊盘的第二半导体器件可面向第一半导体器件的第一表面并且电耦合到第一半导体器件上的第一接合焊盘。 第一半导体器件的第一表面可以与密封剂材料的第一表面共面。

公开(公告)号：US08648477B2

公开(公告)日：2014-02-11

申请号：US12836321

申请日：2010-07-14

Applicant: Dong-han Kim

Inventor： Dong-han Kim

IPC: H01L23/48

CPC classification number: H01L23/49838 ,  G02F1/13452 ,  H01L23/4985 ,  H01L23/50 ,  H01L24/06 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/06155 ,  H01L2224/16225 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/18161 ,  H05K3/323 ,  H05K2201/10136 ,  H05K2201/10446

Abstract: A semiconductor chip package including a film substrate and a semiconductor chip loaded on the semiconductor chip is provided. The semiconductor chip includes a plurality of input pads and a plurality of output pads. A power supply input pad of the input pads is formed at a different edge from an edge of the semiconductor chip where other input pads are formed. The film substrate includes input lines and output lines. The input lines of the film substrate are connected to the corresponding input pads of the semiconductor chip, and the output lines thereof are connected to the corresponding output pads of the semiconductor chip.

Abstract translation: 提供一种半导体芯片封装，其包括装载在半导体芯片上的薄膜基板和半导体芯片。 半导体芯片包括多个输入焊盘和多个输出焊盘。 输入焊盘的电源输入焊盘形成在与形成其它输入焊盘的半导体芯片的边缘不同的边缘处。 薄膜基板包括输入线和输出线。 薄膜基板的输入线连接到半导体芯片的相应的输入焊盘，其输出线连接到半导体芯片的对应的输出焊盘。

公开(公告)号：US08647976B2

公开(公告)日：2014-02-11

申请号：US13348767

申请日：2012-01-12

Applicant: Eun-seok Song ,  Dong-han Kim ,  Hee-seok Lee

Inventor： Eun-seok Song ,  Dong-han Kim ,  Hee-seok Lee

IPC: H01L21/4763

CPC classification number: G01R31/2884 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.

Abstract translation: 公开了半导体封装和测试方法。 封装包括具有顶表面和底表面的衬底，安装在衬底的位于中心的半导体芯片安装区域中的半导体芯片以及设置在衬底的顶表面和底表面上的多个测试焊盘，并且包括第一组测试焊盘 配置在衬底的顶表面和底表面上并且具有在衬底的相应顶部和底部表面上方的第一高度，以及设置在衬底的下表面上并具有大于第一衬底的第二高度的第二组测试焊盘 其中第二组测试垫中的每一个包括附接到其上的焊球。