公开(公告)号：US06297660B2

公开(公告)日：2001-10-02

申请号：US09734514

申请日：2000-12-12

Applicant: Warren M. Farnworth ,  Salman Akram ,  James M. Wark ,  Derek Gochnour

Inventor： Warren M. Farnworth ,  Salman Akram ,  James M. Wark ,  Derek Gochnour

IPC: G01R3126

CPC classification number: G01R1/0466

Abstract: A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for testing components using the carrier, are provided. The carrier includes a base, an interconnect for making temporary electrical connections with the component, and a force applying mechanism for biasing the component against the interconnect. The force applying mechanism includes an elastomeric biasing member adapted to apply a relatively large biasing force during assembly of the carrier and a smaller biasing force in the assembled carrier. The force applying mechanism also includes a pressure plate which can include a cushioning layer with a non-stick surface for contacting the component. In addition, the cushioning layer, and elastomeric biasing member can be made of conductive elastomers to provide an electrical path from a backside of the component.

公开(公告)号：US06253755B1

公开(公告)日：2001-07-03

申请号：US09619943

申请日：2000-07-20

Applicant: James M. Wark ,  Salman Akram

Inventor： James M. Wark ,  Salman Akram

IPC: B28D102

CPC classification number: B28D5/0094

Abstract: A method of dividing a semiconductor wafer into dice, wherein the semiconductor wafer has a circuit side, an underside, and at least one street index that defines the dice, is disclosed. The method includes placing the underside of the wafer on a support having a surface and at least one recess in the surface corresponding to the at least one street index of the wafer, aligning the street index of the semiconductor wafer with the at least one recess in the surface, and dividing the semiconductor wafer along the at least one street index.

Abstract translation: 公开了一种将半导体晶片分成骰子的​​方法，其中半导体晶片具有电路侧，下侧以及限定骰子的至少一个街道指数。 该方法包括将晶片的下侧放置在具有表面的支撑件上，并且在表面中的至少一个凹部对应于晶片的至少一个街道索引，将半导体晶片的街道索引与至少一个凹部对准 并且沿着至少一个街道索引划分半导体晶片。

公开(公告)号：US06239590B1

公开(公告)日：2001-05-29

申请号：US09084732

申请日：1998-05-26

Applicant: Andrew J. Krivy ,  Warren M. Farnworth ,  David R. Hembree ,  Salman Akram ,  James M. Wark ,  John O. Jacobson

Inventor： Andrew J. Krivy ,  Warren M. Farnworth ,  David R. Hembree ,  Salman Akram ,  James M. Wark ,  John O. Jacobson

IPC: G01R104

CPC classification number: G01R35/005 ,  G01R1/073 ,  Y10T29/49197

Abstract: A calibration target for calibrating semiconductor wafer test systems including probe testers and probe card analyzers is provided. Also provided are calibration methods using the calibration target, and a method for fabricating the calibration target. The calibration target includes a substrate with various three dimensional alignment features formed thereon. A first type of alignment feature includes a contrast layer and an alignment fiducial formed on a tip portion thereof. The contrast layer and alignment fiducial are configured for viewing by a viewing device of the probe card analyzer, or the test system, to achieve X-direction and Y-direction calibration. A second type of alignment feature includes a conductive layer formed on a tip portion thereof, which is configured to electrically engage a contact on a check plate of the probe card analyzer, or a probe contact on a probe card of the test system, to achieve Z-direction calibration. The alignment features can be formed by forming raised members on a silicon substrate, and depositing and etching metal layers on the raised members.

Abstract translation: 提供了用于校准包括探针测试仪和探针卡分析仪在内的半导体晶片测试系统的校准目标。 还提供了使用校准目标的校准方法以及用于制造校准目标的方法。 校准目标包括其上形成有各种三维对准特征的基板。 第一类型的对准特征包括形成在其顶端部分上的对比层和对准基准。 对比层和对准基准被配置为通过探针卡分析仪或测试系统的观察装置进行观察，以实现X方向和Y方向校准。 第二类型的对准特征包括形成在其尖端部分上的导电层，其被配置为与探针卡分析器的支撑板上的触点或测试系统的探针卡上的探针接触电接合，以实现 Z方向校准。 对准特征可以通过在硅衬底上形成凸起构件，以及在凸起构件上沉积和蚀刻金属层来形成。

公开(公告)号：US06204678B1

公开(公告)日：2001-03-20

申请号：US09302833

申请日：1999-04-30

Applicant: Salman Akram ,  James M. Wark ,  Warren M. Farnworth

Inventor： Salman Akram ,  James M. Wark ,  Warren M. Farnworth

IPC: G01R173

CPC classification number: G01R31/2886 ,  G01R1/0408

Abstract: An interconnect and system for testing semiconductor dice, and a test method using the interconnect are provided. The interconnect includes a substrate having patterns of contact members for electrically contacting the dice. The interconnect also includes patterns of conductors for providing electrical paths to the contact members. In addition, the interconnect includes contact receiving cavities configured to retain electrical connectors of a testing apparatus in electrical communication with the conductors. A die level test system includes the interconnect mounted to a temporary package for a singulated die. In the die level test system, the interconnect provides direct electrical access from testing circuitry to the die. A wafer level test system includes the interconnect mounted to a probe card fixture of a wafer probe handler. In the wafer level test system, the contact receiving cavities can be configured to support and align the interconnect to the probe card fixture.

Abstract translation: 提供了用于测试半导体晶片的互连和系统，以及使用该互连的测试方法。 互连包括具有用于电接触骰子的接触构件图案的衬底。 互连还包括用于向接触构件提供电路径的导体图案。 此外，互连件包括被配置为保持与导体电连通的测试装置的电连接器的接触接收腔。 芯片级测试系统包括安装到用于单个模具的临时封装的互连。 在芯片级测试系统中，互连提供从测试电路到芯片的直接电接入。 晶片级测试系统包括安装到晶片探测器处理器的探针卡夹具上的互连。 在晶片级测试系统中，触点接收腔可以被配置为支撑并将互连对准到探针卡固定装置。

公开(公告)号：US06200144B1

公开(公告)日：2001-03-13

申请号：US09414203

申请日：1999-10-07

Applicant: James M. Wark

Inventor： James M. Wark

IPC: H01R1200

CPC classification number: G01R31/2808 ,  H01R12/83

Abstract: An apparatus and method for routing all external connection points of a double-sided edge connector of a circuit card to one side of a test tray suitable for testing with a bed of nails, “pogo pin” or similar type of load board for functional testing of said circuit card. A first embodiment of the apparatus includes a pivotally mounted or snap-in removable electrical and mechanical receptacle with a slot or socket suitable for holding a double-sided edge connector of a circuit card in a test tray. The receptacle pivots or is otherwise mounted in the test tray to allow the circuit card to lie co-planar with the test tray, thus providing perpendicular contact to the pins of a bed of nails load board. Another embodiment provides a fixed receptacle mounted vertically that routes all edge connector traces to the bottom surface of the test tray, again, suitable for engaging with a bed of nails-type test board.

Abstract translation: 一种用于将电路卡的双面边缘连接器的所有外部连接点布置到适合于用钉子“pogo pin”或类似类型的用于功能测试的负载板测试的测试托盘的一侧的装置和方法 的电路卡。 该装置的第一实施例包括一个可枢转地安装或卡入式可移除的电气和机械插座，其具有适于将电路卡的双面边缘连接器保持在测试托盘中的槽或插座。 容器枢转或以其他方式安装在测试托盘中，以允许电路卡与测试托盘共面，从而提供与钉子装载板床的销的垂直接触。 另一个实施例提供了垂直安装的固定插座，其将所有边缘连接器迹线路由到测试托盘的底表面，再次适合于与钉子型测试板接合。

公开(公告)号：US6165814A

公开(公告)日：2000-12-26

申请号：US337783

申请日：1999-06-22

Applicant: James M. Wark ,  Salman Akram

Inventor： James M. Wark ,  Salman Akram

IPC: H01L21/98 ,  H01L23/50 ,  H01L23/64 ,  H01L21/44

CPC classification number: H01L25/50 ,  H01L23/13 ,  H01L23/32 ,  H01L23/50 ,  H01L23/642 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/49109 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/10329 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: A semiconductor device including a thin capacitor coupon mounted to the backside of a semiconductor die. When mounted active surface up on a carrier substrate of a multi-chip module, the coupon is secured between the backside of the die and the substrate. When flip-chip connections or direct chip attach are employed between the die and substrate, the coupon is secured to the backside of the die. The coupons may be preformed, or formed on the die in a wafer-scale fabrication process prior to singulation of the dice.

公开(公告)号：US6078186A

公开(公告)日：2000-06-20

申请号：US1409

申请日：1997-12-31

Applicant: David R. Hembree ,  Warren M. Farnworth ,  James M. Wark

Inventor： David R. Hembree ,  Warren M. Farnworth ,  James M. Wark

IPC: G01R31/28 ,  G01R31/02

CPC classification number: G01R31/2886

Abstract: A probe card for testing a semiconductor wafer, a test method, and a test system employing the probe card are provided. The probe card includes: a substrate; an interconnect slidably mounted to the substrate; and a force applying mechanism for biasing contacts on the interconnect into electrical engagement with contacts on the wafer. The force applying mechanism includes spring loaded electrical connectors that provide electrical paths to the interconnect, and generate a biasing force. The biasing force is controlled by selecting a spring constant of the electrical connectors, and an amount of Z-direction overdrive between the probe card and wafer. The probe card also includes a leveling mechanism for leveling the interconnect with respect to the wafer.

公开(公告)号：US6066509A

公开(公告)日：2000-05-23

申请号：US41518

申请日：1998-03-12

Applicant: Salman Akram ,  James M. Wark

Inventor： Salman Akram ,  James M. Wark

IPC: H01L21/00 ,  H01L21/56 ,  H01L21/44

CPC classification number: H01L24/32 ,  H01L21/563 ,  H01L21/6715 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/15151

Abstract: A method and apparatus for attaching a semiconductor device to a substrate. One end of the substrate is elevated to position the substrate and the coupled semiconductor device on an inclined plane. An underfill material is introduced along a wall of the semiconductor device located at the elevated end of the inclined substrate with the underfill material being placed between the substrate and the semiconductor device. An optional but preferred additional step of the invention includes coupling a barrier means to the substrate at a point on the substrate adjacent to a sidewall of the semiconductor device located at the lowest point of the slope created by the inclined substrate. The barrier means prevents the underfill material from spreading beyond the sidewalls of the semiconductor device, particularly in instances where the substrate is inclined at a steep angle.

Abstract translation: 一种用于将半导体器件附接到衬底的方法和装置。 衬底的一端被升高以将衬底和耦合的半导体器件定位在倾斜平面上。 底部填充材料沿着位于倾斜衬底的顶端处的半导体器件的壁被引入，底部填充材料被放置在衬底和半导体器件之间。 本发明的可选但优选的附加步骤包括将屏障装置耦合到衬底上，该衬底与位于由倾斜衬底产生的斜率最低点处的半导体器件的侧壁相邻的衬底上。 阻挡装置防止底部填充材料扩散到半导体器件的侧壁之外，特别是在衬底以陡峭角度倾斜的情况下。

公开(公告)号：US6057597A

公开(公告)日：2000-05-02

申请号：US172451

申请日：1998-10-14

Applicant: Warren M. Farnworth ,  David R. Hembree ,  Derek Gochnour ,  Salman Akram ,  John O. Jacobson ,  James M. Wark ,  Steven G. Thummel

Inventor： Warren M. Farnworth ,  David R. Hembree ,  Derek Gochnour ,  Salman Akram ,  John O. Jacobson ,  James M. Wark ,  Steven G. Thummel

IPC: H01L23/04 ,  H01L23/10 ,  H01L23/12

CPC classification number: H01L23/10 ,  H01L23/04 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195

Abstract: A semiconductor package includes a substrate having one or more dice mounted thereto, and a cover adapted to protect and form a sealed space for the dice. The cover can be pre-fabricated of molded plastic, or stamped metal, and attached to the substrate using a cured seal. A hole can also be provided through the substrate to permit pressure equalization during formation of the seal. The cover can be prefabricated in an enclosed configuration for attachment directly to the substrate, or in a planar configuration for attachment to a peripheral ridge on the substrate. In either embodiment, the cover is removable to permit defective dice to be replaced or repaired.

Abstract translation: 半导体封装包括具有安装在其上的一个或多个裸片的衬底和适于保护并形成用于裸片的密封空间的盖。 盖可以用模制塑料或冲压金属预制，并使用固化的密封件​​附接到基底。 还可以通过基底提供孔，以在形成密封期间允许压力平衡。 盖可以以封闭构造预制成直接附接到基底，或者以平面构造附接到基底上的外围脊。 在任一实施例中，盖可移动以允许更换或修理有缺陷的骰子。

公开(公告)号：US06025730A

公开(公告)日：2000-02-15

申请号：US818456

申请日：1997-03-17

Applicant: Salman Akram ,  James M. Wark ,  Warren M. Farnworth

Inventor： Salman Akram ,  James M. Wark ,  Warren M. Farnworth

IPC: G01R1/04 ,  G01R31/28 ,  G01R1/73

CPC classification number: G01R31/2886 ,  G01R1/0408

Abstract: An interconnect and system for testing semiconductor dice, and a test method using the interconnect are provided. The interconnect includes a substrate having patterns of contact members for electrically contacting the dice. The interconnect also includes patterns of conductors for providing electrical paths to the contact members. In addition, the interconnect includes contact receiving cavities configured to retain electrical connectors of a testing apparatus in electrical communication with the conductors. A die level test system includes the interconnect mounted to a temporary package for a singulated die. In the die level test system, the interconnect provides direct electrical access from testing circuitry to the die. A wafer level test system includes the interconnect mounted to a probe card fixture of a wafer probe handler. In the wafer level test system, the contact receiving cavities can be configured to support and align the interconnect to the probe card fixture.

Abstract translation: 提供了用于测试半导体晶片的互连和系统，以及使用该互连的测试方法。 互连包括具有用于电接触骰子的接触构件图案的衬底。 互连还包括用于向接触构件提供电路径的导体图案。 此外，互连件包括被配置为保持与导体电连通的测试装置的电连接器的接触接收腔。 芯片级测试系统包括安装到用于单个模具的临时封装的互连。 在芯片级测试系统中，互连提供从测试电路到芯片的直接电接入。 晶片级测试系统包括安装到晶片探测器处理器的探针卡夹具上的互连。 在晶片级测试系统中，触点接收腔可以被配置为支撑并将互连对准到探针卡固定装置。