公开(公告)号：US6038592A

公开(公告)日：2000-03-14

申请号：US635048

申请日：1996-04-19

Applicant: Fabrice Verplanken ,  Claude Basso ,  Didier Giroir ,  Jean Calvignac ,  Claude Galand

Inventor： Fabrice Verplanken ,  Claude Basso ,  Didier Giroir ,  Jean Calvignac ,  Claude Galand

IPC: G06F13/00 ,  G06F15/16 ,  G06F15/177 ,  H04L12/18

CPC classification number: H04L12/18

Abstract: An apparatus and method for multicasting messages stored in data buffers of a data storage. Each message is composed of data stored in a plurality of the data buffers. Each data buffer is controlled and mapped to a unique direct control block (DCB) which stores information characterizing the data buffer. By chaining the DCBs variable length, messages can be generated. Indirect control blocks (ICB) stores information characterizing the data or messages duplicated and points to a DCB. A field in the DCB carries a count representing the number of times the message is to be duplicated.

Abstract translation: 一种用于组播存储在数据存储器的数据缓冲器中的消息的装置和方法。 每个消息由存储在多个数据缓冲器中的数据组成。 每个数据缓冲器被控制并映射到唯一的直接控制块（DCB），其存储表征数据缓冲器的信息。 通过链接DCBs可变长度，可以生成消息。 间接控制块（ICB）存储表征复制的数据或消息的信息，并指向DCB。 DCB中的字段表示消息被复制的次数。

公开(公告)号：US5794033A

公开(公告)日：1998-08-11

申请号：US547635

申请日：1995-10-24

Applicant: Jeane-Paul Aldebert ,  Claude Basso ,  Jean Calvignac ,  Paul Chemla ,  Daniel Orsatti ,  Fabrice Verplanken ,  Jean-Claude Zunino

Inventor： Jeane-Paul Aldebert ,  Claude Basso ,  Jean Calvignac ,  Paul Chemla ,  Daniel Orsatti ,  Fabrice Verplanken ,  Jean-Claude Zunino

IPC: G06F13/38 ,  H03K19/177

CPC classification number: G06F13/4256

Abstract: The invention discloses a method and an apparatus for in-line and on-site updating of Field Programmable Gate Arrays with remote loaded configuration data files. Flash EEPROMs which are used because of their non-volatile memories and their high density, are storing more than one configuration data file. The memories are divided in more than one part, each part of the memory for storing one configuration data file. One part of the memory also contains a flag identifying the currently loaded configuration data file. The Flash EPROM's bits being set to one same binary value before any writing operation, including the update of the configuration data file containing the flag. The setting of the bits to said binary value always identifies a valid other configuration data file in order to insure a correct re-loading of the FPGAs in case of reception of an unexpected event leading to an initialization.

Abstract translation: 本发明公开了一种用于使用远程加载的配置数据文件进行现场可编程门阵列的在线和现场更新的方法和装置。 由于其非易失性存储器及其高密度使用的闪存EEPROM存储多个配置数据文件。 存储器分为多个部分，存储器的每个部分用于存储一个配置数据文件。 存储器的一部分还包含标识当前加载的配置数据文件的标志。 闪存EPROM的位在任何写入操作之前被设置为相同的二进制值，包括更新包含该标志的配置数据文件。 对所述二进制值的位的设置总是标识有效的其他配置数据文件，以便在接收到导致初始化的意外事件的情况下确保正确地重新加载FPGA。

公开(公告)号：US5768273A

公开(公告)日：1998-06-16

申请号：US547828

申请日：1995-11-01

Applicant: Ange Aznar ,  Jean Calvignac ,  Daniel Orsatti ,  Dominique Rigal ,  Fabrice Verplanken

Inventor： Ange Aznar ,  Jean Calvignac ,  Daniel Orsatti ,  Dominique Rigal ,  Fabrice Verplanken

IPC: H04L12/931 ,  H04L12/935 ,  H04J3/22

CPC classification number: H04L49/30 ,  H04L49/205 ,  H04L49/3009

Abstract: An ATM switch includes one or more adapters having input ports and/or output ports and a switching fabric for switching Asynchronous Transfer Mode (ATM) cells received at the input ports to the output ports. To maintain switch throughput, cells are categorized either as real time (high priority) or non-real time (lower priority) cells. High priority cells are processed using a first set of cell processing logic at a rate at least equal to the rate at which the cells are received on the input ports. Lower priority cells are processed using a second set of cell processing logic only when no high priority cells are being processed.

Abstract translation: ATM交换机包括具有输入端口和/或输出端口的一个或多个适配器，以及用于将在输入端口处接收的异步传输模式（ATM）单元切换到输出端口的交换结构。 为了保持交换机吞吐量，小区被分类为实时（高优先级）或非实时（较低优先级）小区。 使用第一组信元处理逻辑以至少等于在输入端口上接收信元的速率的速率处理高优先级信元。 仅当不处理高优先级单元时，才使用第二组单元处理逻辑来处理低优先级单元。

公开(公告)号：US5684797A

公开(公告)日：1997-11-04

申请号：US548030

申请日：1995-10-25

Applicant: Ange Aznar ,  Jean Calvignac ,  Daniel Orsatti ,  Dominique Rigal ,  Fabrice Verplanken

Inventor： Ange Aznar ,  Jean Calvignac ,  Daniel Orsatti ,  Dominique Rigal ,  Fabrice Verplanken

IPC: H04L12/18 ,  H04L12/931 ,  H04L12/935 ,  H04L12/56

CPC classification number: H04L49/201 ,  H04L49/30

Abstract: A multicasting apparatus and method for an Asynchronous Transfer Mode (ATM) switch is described, which uses a single target port (TP) vector attached to each outgoing ATM cell. The target port vector contains identifiers of each port to which the cell has to be transmitted. After transmission of the cell, the identifier relating to respective target port is erased from the TP vector. Hence the TP vector contains only identifiers of target port to which the cell has not yet been transmitted. When the TP vector contains no identifiers, the storage location at which the ATM cell is stored during the transmission, is freed for another cell. Unicast and multicast traffic are treated identically.

Abstract translation: 描述了用于异步传输模式（ATM）交换机的多播设备和方法，其使用附接到每个输出ATM信元的单个目标端口（TP）向量。 目标端口向量包含单元必须发送到的每个端口的标识符。 在小区的传输之后，从TP向量中删除与各目标端口有关的标识符。 因此，TP向量仅包含小区尚未被发送到的目标端口的标识符。 当TP向量不包含标识符时，传输期间存储ATM信元的存储位置被释放用于另一小区。 单播和多播流量处理相同。

公开(公告)号：US5557266A

公开(公告)日：1996-09-17

申请号：US206363

申请日：1994-03-07

Applicant: Jean Calvignac ,  Pierre Huon ,  Daniel Orsatti ,  Gilles Toubol ,  Fabrice Verplanken

Inventor： Jean Calvignac ,  Pierre Huon ,  Daniel Orsatti ,  Gilles Toubol ,  Fabrice Verplanken

IPC: H04L12/933 ,  H04L12/935 ,  H04L12/937 ,  H04L29/00 ,  H03K17/00

CPC classification number: H04L49/15 ,  H04L29/00 ,  H04L49/103 ,  H04L49/254 ,  H04L49/3027

Abstract: A system for cascading data switches in a communication node allows for transfer of data among a plurality of adapters (30-i), expanding a moderate low cost switch 31-1 with additional hardware (31-2, 31-3, 31-4) to interconnect more adapters. The data transfers are performed by a plurality of Burst Relaying Cascaders (32-i) which connect the plurality of switches (31-i). A similar interface connect each adapter to the switch. A set of address information is used by the system to route the data from the source adapter to the target adapter, allowing navigation among the intermediate switches. Each interface contains a table where the address of every adapter of the whole system could be constructed dynamically at each communication node configuration.

Abstract translation: 用于在通信节点中级联数据交换的系统允许在多个适配器（30-i）之间传输数据，用附加硬件（31-2,31-3-3,34-4）扩展适度的低成本开关31-1 ）来互连更多适配器。 数据传送由连接多个开关（31-i）的多个突发中继级联（32-i）执行。 类似的接口将每个适配器连接到交换机。 系统使用一组地址信息将数据从源适配器路由到目标适配器，允许在中间交换机之间导航。 每个接口包含一个表，其中可以在每个通信节点配置下动态构建整个系统的每个适配器的地址。

公开(公告)号：US5491815A

公开(公告)日：1996-02-13

申请号：US120112

申请日：1993-09-10

Applicant: Claude Basso ,  Jean Calvignac ,  Tan T. Pham ,  Charles Rheinart

Inventor： Claude Basso ,  Jean Calvignac ,  Tan T. Pham ,  Charles Rheinart

IPC: G06F1/14 ,  G06F9/48 ,  G06F11/30 ,  H04L29/06 ,  G06F1/04

CPC classification number: G06F9/4825 ,  H04L29/06

Abstract: A system for providing a plurality of timers to perform the timing of event occurrences wherein, for each event, there corresponds a timer control block which stores in its time-flag field (Tf) an indication of whether the timer control block is chained or unchained, running or stopped, in its time-out field (Tv) the expiration time interval and in its time-stamp field (Ts) the current time as a reference at each interruption. The timer control blocks are chained by a one-way link according to their expiration times in such a way that each timer chain contains the timer control blocks whose events will occur at the same time. A cyclic table of index values classifies the timer chains according to their expiration times. When a START operation is requested for an event which has to occur at a time-out value, an index is computed according to the Tv and the current time in order to insert its corresponding timer control block at the head of the timer chain pointed to by the index; the timer control block storing the state of CHAINED-RUNNING in its time-flag and the current time in its time-stamp. If the timer control block is already chained, then the time-stamp is updated to the current time and the time-flag to RUNNING. Whenever a RESTART operation is requested for an event which has not occurred, the time-stamp of the corresponding timer control block is updated to the value of the current time. Whenever a STOP operation is requested before the event has occurred, the time-flag is updated to STOP. The time-stamps and the time-flags are updated according to the START, STOP and RESTART operations, the current index of the cyclic table is incremented at each timer-tick to delete the timer control blocks of the chain whose events have occurred or whose time-out values have expired, and to insert new timer control blocks in the new timer chain for those tasks which have been interrupted and whose events have not occurred yet.

公开(公告)号：US5432910A

公开(公告)日：1995-07-11

申请号：US909884

申请日：1992-07-07

Applicant: Kenneth J. Barker ,  George M. Calhoun ,  Jean Calvignac ,  Rene Castel ,  Jean C. Dispensa ,  Yves Huchet ,  Edward S. Suffern ,  Ruggero Ulivastro

Inventor： Kenneth J. Barker ,  George M. Calhoun ,  Jean Calvignac ,  Rene Castel ,  Jean C. Dispensa ,  Yves Huchet ,  Edward S. Suffern ,  Ruggero Ulivastro

IPC: G06F13/12 ,  G06F13/28

CPC classification number: G06F13/128 ,  G06F13/124

Abstract: The connection capability of a communication controller is extended. The communication controller includes a central control unit CCU, running a network control program NCP stored in a memory having a direct memory access facility through a DMA bus. The input/output bus of the communication controller and DMA bus are connected to line adapters, and channel adapters and a controller extension through a coupler which allows additional adapters to be connected to the controller. At initialization, a table is built into a coupler memory, which is then used in steady state mode for controlling the transmission of the messages to the additional users and the reception of the messages from the additional users, by improving the buffer unchaining and chaining processes into the NCP memory.

Abstract translation: 通信控制器的连接能力得到延长。 通信控制器包括中央控制单元CCU，其通过DMA总线运行存储在具有直接存储器访问设施的存储器中的网络控制程序NCP。 通信控制器和DMA总线的输入/输出总线通过耦合器连接到线路适配器，通道适配器和控制器扩展，允许其他适配器连接到控制器。 在初始化时，一个表被内置到一个耦合器存储器中，然后在稳态模式下使用这种方式，通过改进缓冲器解链和链接过程来控制消息到附加用户的传输和来自附加用户的消息的接收 进入NCP内存。

公开(公告)号：US5392401A

公开(公告)日：1995-02-21

申请号：US5425

申请日：1993-01-21

Applicant: Gerard Barucchi ,  Jean Calvignac ,  Daniel Orsatti ,  Andre Tracol

Inventor： Gerard Barucchi ,  Jean Calvignac ,  Daniel Orsatti ,  Andre Tracol

IPC: G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F13/00 ,  G06F13/14

CPC classification number: G06F15/17375

Abstract: The system performs an optimized number of simultaneous transfers of data packets between pairs of units comprising an origin unit and a target unit selected among N data processing units (8). Each data processing unit comprises a set of outbound queues with one outbound queue associated with each one of the data processing units to which it may send data packets, for storing the data packets to be sent by the data processing unit to the data processing unit associated with said one outbound queue. The transfers are performed during a time burst Ti+1 by data switch 6 under control of switching control signals sent to data switch by the units on lines 16-1 to 16-N in response to control out signals generated by scheduler 4 during previous burst time Ti. The scheduler runs a selection algorithm which gives each unit an equal probability to be selected as origin unit in a given period.

Abstract translation: 该系统在包括从N个数据处理单元（8）中选择的原始单元和目标单元的单元对之间执行数据分组的优化数量的同时传送。 每个数据处理单元包括一组出站队列，其中一个出站队列与其可以发送数据分组的数据处理单元中的每一个相关联，用于存储要由数据处理单元发送到数据处理单元的数据分组 有一个出站队列。 响应于在先前的突发期间由调度器4产生的控制信号，在数据交换机6的时间突发Ti + 1的控制下，在由线路16-1至16-N上的单元发送到数据交换的切换控制信号的情况下， 时间Ti 调度器运行选择算法，其给出每个单位在给定时间段内作为原始单位的相等概率。

公开(公告)号：US5333269A

公开(公告)日：1994-07-26

申请号：US965554

申请日：1992-10-23

Applicant: Jean Calvignac ,  Jean-Pierre Lips ,  Jean-Marc Millet ,  Jean-Marie Munier ,  Bernard Naudin

Inventor： Jean Calvignac ,  Jean-Pierre Lips ,  Jean-Marc Millet ,  Jean-Marie Munier ,  Bernard Naudin

IPC: G06F15/16 ,  G06F13/38 ,  G06F13/42 ,  G06F15/167 ,  G06F15/177 ,  H04L12/40

CPC classification number: G06F15/167 ,  G06F9/544

Abstract: A device for interconnecting source users and destination users includes a common bus to which a memory with a plurality of independent buffers, a memory interface (22) and a central control apparatus (26) are connected. The memory interface (22) receives messages from source users, stores the messages in selected buffers and chains the buffers together. The central control apparatus generates inbound message queues and outbound message queues in response to commands which it receives from the memory interface.

Abstract translation: 用于互连源用户和目的用户的设备包括公共总线，具有多个独立缓冲器的存储器，存储器接口（22）和中央控制设备（26）连接到该总线。 存储器接口（22）从源用户接收消息，将消息存储在所选择的缓冲器中并将缓冲器链接在一起。 中央控制装置响应于从存储器接口接收到的命令，生成入站消息队列和出站消息队列。

公开(公告)号：US5237572A

公开(公告)日：1993-08-17

申请号：US830128

申请日：1992-01-31

Applicant: Mohamed Badaoui ,  Jean Calvignac ,  Guy Carle ,  Christian Garcia ,  Pierre Vachee

Inventor： Mohamed Badaoui ,  Jean Calvignac ,  Guy Carle ,  Christian Garcia ,  Pierre Vachee

IPC: G06F13/38

CPC classification number: G06F13/385

Abstract: An Active Remote Module (ARM) attaches end user devices to any port of a multiport communications processing unit. The ARM includes circuit arrangements which receive serial streams of data and clock information which are arranged into data slots, control slots and outband slot carrying characteristic information, including ARM address, ARM type, end user data rate, etc., about the ARM and the end user devices. By issuing selective commands, a line adapter in the multiport communications processing unit is made aware of the user devices connected to its port and structure the data to meet the requirement of the attached end user devices.

Abstract translation: 主动远程模块（ARM）将终端用户设备连接到多端口通信处理单元的任何端口。 ARM包括电路布置，其接收串行数据流和时钟信息，这些数据和时钟信息被布置成关于ARM和ARM的数据时隙，控制时隙和携带特征信息的带外特征信息，包括ARM地址，ARM类型，最终用户数据速率等 最终用户设备。 通过发出选择性命令，使多端口通信处理单元中的线路适配器知道连接到其端口的用户设备并且构造数据以满足所附连接的终端用户设备的要求。