公开(公告)号：US20060274479A1

公开(公告)日：2006-12-07

申请号：US11146587

申请日：2005-06-07

Applicant: Kaladhar Radhakrishnan ,  Nicholas Holmberg ,  Joel Auernheimer ,  Dustin Wood

Inventor： Kaladhar Radhakrishnan ,  Nicholas Holmberg ,  Joel Auernheimer ,  Dustin Wood

IPC: H01G4/38 ,  H01G4/06

CPC classification number: H01G4/30 ,  H01G4/232

Abstract: An array capacitor is provided. The array capacitor includes a plurality of ground planes inside a dielectric substrate, and a plurality of ground vias. The ground vias electrically connect the ground planes together. Further, the ground vias are connected to ground terminals of the array capacitor to enable electrical coupling between the ground planes and the ground terminals. The array capacitor further includes a plurality of power planes inside the dielectric substrate. The power planes and the ground planes are arranged alternatively inside the dielectric substrate. Each power plane comprises a plurality of power-plane-sections which are mutually electrically isolated. The array capacitor also includes a plurality of power vias which electrically connect the power planes together. Further, the power vias are connected to power terminals of the array capacitor to enable electrical coupling between the power planes and power terminals.

Abstract translation: 提供阵列电容器。 阵列电容器包括介电衬底内的多个接地层，以及多个接地通孔。 接地通孔将接地层电连接在一起。 此外，接地通孔连接到阵列电容器的接地端子，以实现接地层和接地端子之间的电耦合。 阵列电容器还包括介电衬底内的多个电源层。 电源平面和接地平面交替布置在电介质基片内。 每个电力平面包括彼此电隔离的多个电力平面部分。 阵列电容器还包括将电源平面电连接在一起的多个电源通孔。 此外，电源通孔连接到阵列电容器的电源端子，以实现电力平面和电源端子之间的电耦合。

公开(公告)号：US20050285243A1

公开(公告)日：2005-12-29

申请号：US10880150

申请日：2004-06-28

Applicant: Brent Stone ,  Dustin Wood ,  Kaladhar Radhakrishnan

Inventor： Brent Stone ,  Dustin Wood ,  Kaladhar Radhakrishnan

IPC: H01L23/02 ,  H01L23/498 ,  H01L23/50

CPC classification number: H01L23/50 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit package includes a first capacitor supported by a surface of a substrate, and a second capacitor supported by the surface of the substrate. The first capacitor is within a die shadow region, and the second capacitor lies outside of the die shadow region.

Abstract translation: 集成电路封装包括由衬底的表面支撑的第一电容器和由衬底的表面支撑的第二电容器。 第一电容器在阴影区域内，第二电容器位于阴影阴影区域的外部。

公开(公告)号：US20050112842A1

公开(公告)日：2005-05-26

申请号：US10720812

申请日：2003-11-24

Applicant: Jung Kang ,  Kaladhar Radhakrishnan ,  Shamala Chickamenahalli

Inventor： Jung Kang ,  Kaladhar Radhakrishnan ,  Shamala Chickamenahalli

IPC: H01L21/00 ,  H01L21/30 ,  H01L23/31 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/5222 ,  H01L23/5228 ,  H01L24/48 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An embodiment of the present invention is a technique to integrate passive components in a die assembly. A capacitor, inductor, or resistor is integrated on a spacer between upper and lower dies in stacked dies. Conductors are attached to the capacitor, inductor or resistor to connect the capacitor, inductor, or resistor to at least one of the upper and lower dies.

Abstract translation: 本发明的一个实施例是一种在模具组件中集成无源部件的技术。 电容器，电感器或电阻器集成在堆叠模具中的上模和下模之间的间隔件上。 导体连接到电容器，电感器或电阻器，以将电容器，电感器或电阻器连接到上模具和下模具中的至少一个。