公开(公告)号：US20130062774A1

公开(公告)日：2013-03-14

申请号：US13228011

申请日：2011-09-08

Applicant: Chung-Chi Ko ,  Chia-Cheng Chou ,  Shing-Chyang Pan ,  Keng-Chu Lin ,  Shwang-Ming Jeng

Inventor： Chung-Chi Ko ,  Chia-Cheng Chou ,  Shing-Chyang Pan ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/31144 ,  H01L21/321 ,  H01L21/76811 ,  H01L21/76813

Abstract: A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.

Abstract translation: 一种方法包括在低k电介质层上形成金属硬掩模。 形成金属硬掩模的步骤包括沉积金属硬掩模的子层，并对金属硬掩模的子层进行等离子体处理。 将金属硬掩模图案化以形成开口。 蚀刻低k电介质层以形成沟槽，其中使用金属硬掩模作为蚀刻掩模进行蚀刻步骤。

公开(公告)号：US20130052818A1

公开(公告)日：2013-02-28

申请号：US13220245

申请日：2011-08-29

Applicant: Po-Cheng Shih ,  Chung-Chi Ko ,  Keng-Chu Lin

Inventor： Po-Cheng Shih ,  Chung-Chi Ko ,  Keng-Chu Lin

IPC: H01L21/768

CPC classification number: H01L21/76811 ,  H01L21/02167 ,  H01L21/02271 ,  H01L21/31144 ,  H01L21/76813

Abstract: A method includes forming a hard mask over a low-k dielectric layer, and patterning the hard mask to form an opening. A stress tuning layer is formed over the low-k dielectric layer and in physical contact with the hard mask. The stress tuning layer has an inherent stress, wherein the inherent stress is a near-zero stress or a tensile stress. The low-k dielectric layer is etched to form a trench aligned to the opening, wherein the step of etching is performed using the hard mask as an etching mask.

Abstract translation: 一种方法包括在低k电介质层上形成硬掩模，并对硬掩模进行图案化以形成开口。 应力调整层形成在低k电介质层上并与硬掩模物理接触。 应力调整层具有固有应力，其中固有应力为近零应力或拉伸应力。 蚀刻低k电介质层以形成与开口对准的沟槽，其中使用硬掩模作为蚀刻掩模进行蚀刻步骤。

公开(公告)号：US08354346B2

公开(公告)日：2013-01-15

申请号：US13179139

申请日：2011-07-08

Applicant: Chih-Hao Chen ,  Chia-Cheng Chou ,  Ming-Chung Liang ,  Keng-Chu Lin ,  Tzu-Li Lee

Inventor： Chih-Hao Chen ,  Chia-Cheng Chou ,  Ming-Chung Liang ,  Keng-Chu Lin ,  Tzu-Li Lee

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/31138

Abstract: A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.

Abstract translation: 提供了一种通过降低RC延迟时间来提高集成电路性能的系统和方法。 优选的实施方案包括在低k电介质蚀刻之后向灰/冲击等离子体工艺中添加反应性蚀刻气体。 说明性实施例实现了在低k电介质蚀刻期间形成的损伤层的去除。

公开(公告)号：US20120077339A1

公开(公告)日：2012-03-29

申请号：US12893399

申请日：2010-09-29

Applicant: Chung-Chi KO ,  Chia Cheng CHOU ,  Keng-Chu LIN ,  Joung-Wei LIOU ,  Shwang-Ming JENG ,  Mei-Ling CHEN

Inventor： Chung-Chi KO ,  Chia Cheng CHOU ,  Keng-Chu LIN ,  Joung-Wei LIOU ,  Shwang-Ming JENG ,  Mei-Ling CHEN

IPC: H01L21/768 ,  H05B1/00

CPC classification number: H01L21/768 ,  H01L21/02126 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/70 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76828

Abstract: A method of and apparatus for forming interconnects on a substrate includes etching patterns in ultra-low k dielectric and removing moisture from the ultra-low k dielectric using active energy assist baking. During active energy assist baking, the ultra-low k dielectric is heated and exposed to light having only wavelengths greater than 400 nm for about 1 to about 20 minutes at a temperature of about 300 to about 400 degrees Celsius. The active energy assist baking is performed after wet-cleaning or after chemical mechanical polishing, or both.

Abstract translation: 用于在衬底上形成互连的方法和装置包括在超低k电介质中的蚀刻图案，并且使用主动能量辅助烘烤从超低k电介质去除湿气。 在活性能量辅助烘烤期间，在约300至约400摄氏度的温度下，超低k电介质被加热并暴露于仅具有大于400nm波长的光约1至约20分钟。 活性能量辅助烘烤在湿清洗或化学机械抛光之后进行，或两者都进行。

公开(公告)号：US20110263127A1

公开(公告)日：2011-10-27

申请号：US13179139

申请日：2011-07-08

Applicant: Chih-Hao Chen ,  Chia-Cheng Chou ,  Ming-Chung Liang ,  Keng-Chu Lin ,  Tzu-Li Lee

Inventor： Chih-Hao Chen ,  Chia-Cheng Chou ,  Ming-Chung Liang ,  Keng-Chu Lin ,  Tzu-Li Lee

IPC: H01L21/311

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/31138

Abstract: A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.

Abstract translation: 提供了一种通过降低RC延迟时间来提高集成电路性能的系统和方法。 优选的实施方案包括在低k电介质蚀刻之后向灰/冲击等离子体工艺中添加反应性蚀刻气体。 说明性实施例实现了在低k电介质蚀刻期间形成的损伤层的去除。

公开(公告)号：US07968451B2

公开(公告)日：2011-06-28

申请号：US12509039

申请日：2009-07-24

Applicant: Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

Inventor： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

IPC: H01L21/4763

CPC classification number: H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon.

Abstract translation: 一种用于制造集成电路的方法包括在半导体衬底上形成低k电介质层，蚀刻低k电介质层以形成开口，并且用气体有机化学品处理低k电介质层以引起第 低k电介质层和气态有机化学品。 气态有机化学物质不含硅。

公开(公告)号：US07723226B2

公开(公告)日：2010-05-25

申请号：US11654427

申请日：2007-01-17

Applicant: Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

Inventor： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

IPC: H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

Abstract translation: 提出了双层多孔低介电常数（低k）互连结构及其制造方法。 具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积的介电层和顶部沉积的介电层。 底层和顶层具有相同的原子组成，但是较高的介电常数值k。 底部介电层用作顶部介电层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。 制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。 固化过程在底部电介质层中留下的孔隙密度低于顶部介电层中留下的孔密度，这导致底部介电层中较高的介电常数k。

公开(公告)号：US20090286394A1

公开(公告)日：2009-11-19

申请号：US12509039

申请日：2009-07-24

Applicant: Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

Inventor： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L21/306

CPC classification number: H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon.

Abstract translation: 一种用于制造集成电路的方法包括在半导体衬底上形成低k电介质层，蚀刻低k电介质层以形成开口，并且用气体有机化学品处理低k电介质层以引起第 低k电介质层和气态有机化学品。 气态有机化学物质不含硅。

公开(公告)号：US20080272493A1

公开(公告)日：2008-11-06

申请号：US11797310

申请日：2007-05-02

Applicant: Chung-Chi Ko ,  Chia-Cheng Chou ,  Zhen-Cheng Wu ,  Keng-Chu Lin ,  Shwang-Ming Jeng

Inventor： Chung-Chi Ko ,  Chia-Cheng Chou ,  Zhen-Cheng Wu ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC: H01L23/52

CPC classification number: H01L23/53295 ,  H01L21/563 ,  H01L21/7682 ,  H01L21/76825 ,  H01L23/5329 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: A semiconductor device is disclosed. The device includes a substrate, a first porous SiCOH dielectric layer, a second porous SiCOH dielectric layer, and an oxide layer. The first porous SiCOH dielectric layer overlies the substrate. The second porous SiCOH dielectric layer overlies the first porous SiCOH dielectric layer. The oxide layer overlies the second porous SiCOH dielectric layer. The atomic percentage of carbon in the second porous SiCOH dielectric layer is between 16% and 22% of that in the first porous SiCOH dielectric layer.

Abstract translation: 公开了一种半导体器件。 该器件包括衬底，第一多孔SiCOH电介质层，第二多孔SiCOH电介质层和氧化物层。 第一多孔SiCOH介电层覆盖在基底上。 第二多孔SiCOH介电层覆盖第一多孔SiCOH介电层。 氧化物层覆盖第二多孔SiCOH介电层。 第二多孔SiCOH介电层中的碳的原子百分比在第一多孔SiCOH介电层中的原子百分比为16％至22％。

公开(公告)号：US07405481B2

公开(公告)日：2008-07-29

申请号：US11004065

申请日：2004-12-03

Applicant: Keng-Chu Lin ,  Yung-Cheng Lu ,  Shwang-Ming Cheng

Inventor： Keng-Chu Lin ,  Yung-Cheng Lu ,  Shwang-Ming Cheng

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an integrated circuit chip, a conductive line is formed in a first IMD layer. The conductive line is formed of a conductive line material that tends to form an oxide when exposed to an oxygen-containing substance. A glue layer is formed on the conductive line. The glue layer is formed of a non-oxygen-containing material capable of providing an oxygen barrier over the conductive line. The glue layer has a hardness greater than that of the conductive line. The glue layer preferably has a thickness between about 15 angstroms and about 75 angstroms. The etch stop layer is formed on the glue layer. The etch stop layer has a hardness greater than that of the glue layer. A second IMD layer is formed on the etch stop layer. The etch stop layer and/or the second IMD layer may be formed with a material comprising oxygen without oxidizing the conductive line.

Abstract translation: 在集成电路芯片中，在第一IMD层中形成导线。 导电线由暴露于含氧物质时易于形成氧化物的导电线材料形成。 在导电线上形成胶层。 胶层由能够在导电线上提供氧阻隔的非含氧材料形成。 胶层的硬度大于导电线的硬度。 胶层优选地具有在约15埃至约75埃之间的厚度。 蚀刻停止层形成在胶层上。 蚀刻停止层的硬度大于胶层的硬度。 在蚀刻停止层上形成第二IMD层。 蚀刻停止层和/或第二IMD层可以由包含氧的材料形成而不氧化导电线。