公开(公告)号：US20050110066A1

公开(公告)日：2005-05-26

申请号：US10718666

申请日：2003-11-24

Applicant: Ming-Cheng Chang

Inventor： Ming-Cheng Chang

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10867 ,  H01L27/10897

Abstract: Disclosed is a deep trench structure for a semiconductor memory device. The deep trench in accordance with the present invention has a cross section communicating with two difference active areas, which are respectively connected to two adjacent bit lines of the semiconductor memory device.

Abstract translation: 公开了一种用于半导体存储器件的深沟槽结构。 根据本发明的深沟槽具有与两个差分有效区域通信的横截面，其两个分别连接到半导体存储器件的两个相邻位线。

公开(公告)号：US20050082590A1

公开(公告)日：2005-04-21

申请号：US10972505

申请日：2004-10-25

Applicant: Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

Inventor： Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/1087 ,  H01L27/10832 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66181

Abstract: A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.

公开(公告)号：US06801462B2

公开(公告)日：2004-10-05

申请号：US10612857

申请日：2003-07-03

Applicant: Ming Cheng Chang ,  Jeng-Ping Lin ,  Tie Jiang Wu

Inventor： Ming Cheng Chang ,  Jeng-Ping Lin ,  Tie Jiang Wu

IPC: G11C700

CPC classification number: H01L27/10894 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  H01L22/34 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/10891 ,  H01L27/10897

Abstract: A test device and method for detecting alignment of word lines and deep trench capacitors in DRAM devices. In the test device, parallel first and second bar-type deep trenches capacitors are disposed in the scribe line region. The first and second bar-type deep trenches capacitors extend to the first and second pairs of memory cells in the memory region adjacent to the first active area respectively. The first and second bar-type deep trenches capacitors are electrically coupled to bit line contacts of the first and second pairs of memory cells respectively. First and second transistors have sources coupled to the first and second bar-type deep trenches capacitors respectively. A first bit line contact is electrically coupled to drains of the first and second transistors.

Abstract translation: 用于检测DRAM器件中的字线和深沟槽电容器的对准的测试装置和方法。 在测试装置中，平行的第一和第二条形深沟槽电容器设置在划线区域中。 第一和第二条形深沟槽电容器分别延伸到与第一有效区域相邻的存储器区域中的第一和第二对存储单元。 第一和第二条形深沟槽电容器分别电耦合到第一和第二对存储器单元的位线触点。 第一和第二晶体管分别具有耦合到第一和第二条形深沟槽电容器的源极。 第一位线接触件电耦合到第一和第二晶体管的漏极。

公开(公告)号：US06788598B2

公开(公告)日：2004-09-07

申请号：US10448661

申请日：2003-05-30

Applicant: Ming-Cheng Chang ,  Tie-Jiang Wu ,  Jeng-Ping Lin ,  Tse-Main Kuo ,  Hsu-Cheng Fan

Inventor： Ming-Cheng Chang ,  Tie-Jiang Wu ,  Jeng-Ping Lin ,  Tse-Main Kuo ,  Hsu-Cheng Fan

IPC: G11C700

CPC classification number: H01L27/10861 ,  G11C11/401 ,  G11C29/50 ,  G11C2029/5002 ,  G11C2029/5004 ,  H01L22/34 ,  H01L27/0207 ,  H01L27/10891 ,  H01L29/66181

Abstract: A test key disposed on a scribe line of a wafer. The test key includes: two active areas disposed on the substrate; two first deep trench capacitors disposed on the substrate outside the two active areas; a rectangular active word line disposed on the substrate covering the first deep trench capacitors and the active areas; first and second passing word lines disposed on one side of the rectangular active word line and across the parallel active areas; a third passing word line disposed on another side of the rectangular active word line and across another end of the two active areas; two second deep trench capacitors disposed on the substrate under where the two first passing word lines overlap the two active areas; and four contacts disposed on the first active areas between the first and second word lines and between the third and the rectangular active word line.

公开(公告)号：US06536915B1

公开(公告)日：2003-03-25

申请号：US10072928

申请日：2002-02-12

Applicant: Ming-Cheng Chang

Inventor： Ming-Cheng Chang

IPC: F21V500

CPC classification number: F21V15/01 ,  F21S4/10 ,  F21S4/20

Abstract: A lamp string comprises a plurality of serially connected lamp units. Each lamp unit comprises a casing, two base plates respectively mounted in two ends of the casing, an illuminating member mounted in the casing, at least one metallic bar extending between the base plates and electrically connected to the illuminating member, and two end covers removably attached to the ends of the casing for closing the casing. Two adjacent ones of the lamp units are electrically connected by at least one wire that is electrically connected to the illuminating member and the metallic bar. A soft tube may be provided to enclose the wire.

Abstract translation: 灯串包括多个串联的灯单元。 每个灯单元包括壳体，分别安装在壳体的两端的两个基板，安装在壳体中的照明构件，在基板之间延伸并电连接到照明构件的至少一个金属杆，以及可拆卸地两个端盖 附接到壳体的端部以关闭壳体。 两个相邻的灯单元通过电连接到照明构件和金属棒的至少一根导线电连接。 可以提供软管以包围线。

公开(公告)号：USD425232S

公开(公告)日：2000-05-16

申请号：US99656

申请日：1999-01-25

Applicant: Ming Cheng Chang

Designer： Ming Cheng Chang

公开(公告)号：US08426925B2

公开(公告)日：2013-04-23

申请号：US12945536

申请日：2010-11-12

Applicant: Ying Cheng Chuang ,  Ping Cheng Hsu ,  Sheng Wei Yang ,  Ming Cheng Chang ,  Hung Ming Tsai

Inventor： Ying Cheng Chuang ,  Ping Cheng Hsu ,  Sheng Wei Yang ,  Ming Cheng Chang ,  Hung Ming Tsai

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/76224 ,  H01L27/10876 ,  H01L27/10891

Abstract: A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.

Abstract translation: 存储器件包括多个隔离件和沟槽填料，沿方向交替排列，隔离件和沟槽填料之间的多个台面结构，以及各自覆盖相应台面的侧表面的多个字线。 在本发明的一个实施例中，在沟槽填料的方向上测量的宽度小于隔离层的宽度，每个台面结构包括至少一个成对的源极/漏极区域和对应于配对源极的至少一个沟道基极区域 /漏极区域，并且每个字线在台面结构的侧表面上，与相应的隔离相邻，并且被布置为与通道基底区域相邻。

公开(公告)号：US20120108047A1

公开(公告)日：2012-05-03

申请号：US12917339

申请日：2010-11-01

Applicant: Ying-Cheng Chuang ,  Hung-Ming Tsai ,  Sheng-Wei Yang ,  Ping-Cheng Hsu ,  Ming-Cheng Chang

Inventor： Ying-Cheng Chuang ,  Hung-Ming Tsai ,  Sheng-Wei Yang ,  Ping-Cheng Hsu ,  Ming-Cheng Chang

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L27/10876 ,  H01L21/28531 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888

Abstract: A method of forming a conductive contact includes forming a structure comprising an upper surface joining with a sidewall surface. The sidewall surface contains elemental-form silicon. Silicon is epitaxially grown from the sidewall surface. Dielectric material is formed over the upper surface and the epitaxially-grown silicon. A conductive contact is formed through the dielectric material to conductively connect with the upper surface.

Abstract translation: 形成导电接触的方法包括形成包括与侧壁表面接合的上表面的结构。 侧壁表面含有元素型硅。 硅从侧壁表面外延生长。 电介质材料形成在上表面和外延生长的硅上。 通过电介质材料形成导电接触，以与上表面导电连接。

公开(公告)号：US20100200903A1

公开(公告)日：2010-08-12

申请号：US12767639

申请日：2010-04-26

Applicant: Ming-Cheng Chang ,  Chih-Hsiung Hung ,  Mao-Ying Wang ,  Wei-Hui Hsu

Inventor： Ming-Cheng Chang ,  Chih-Hsiung Hung ,  Mao-Ying Wang ,  Wei-Hui Hsu

IPC: H01L29/788

CPC classification number: H01L29/66583 ,  H01L21/28273 ,  H01L29/512 ,  H01L29/7887

Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

Abstract translation: 提供一种非易失性存储器件及其制造方法。 非易失性存储器件的制造方法包括提供衬底。 在衬底中形成隧道绝缘层和第一导电层。 通过第一导电层和隧道绝缘层形成沟槽，其中衬底的一部分从沟槽露出。 在沟槽中形成第一绝缘层。 第二绝缘层形成在第一绝缘层的侧壁上。 第三绝缘层顺应地形成在沟槽中，覆盖沟槽底部的第一绝缘层和沟槽侧壁上的第二绝缘层，其中侧壁上的第三绝缘层的厚度比在 沟渠的底部。 控制栅极形成在沟槽中的第三绝缘层上。

公开(公告)号：US20090108321A1

公开(公告)日：2009-04-30

申请号：US11948947

申请日：2007-11-30

Applicant: Ming-Cheng Chang ,  Wei-Ming Liao ,  Jer-Chyi Wang ,  Chien-Chang Huang

Inventor： Ming-Cheng Chang ,  Wei-Ming Liao ,  Jer-Chyi Wang ,  Chien-Chang Huang

IPC: H01L29/788

CPC classification number: G11C16/0458 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/7887

Abstract: A flash memory is provided. The flash memory includes a substrate, a first insulation layer formed on the substrate, a control gate disposed on the first insulation layer, and two floating gates coplanar with the substrate respectively disposed on both sides of the control gate.

Abstract translation: 提供闪存。 闪速存储器包括基板，形成在基板上的第一绝缘层，设置在第一绝缘层上的控制栅极和与分别设置在控制栅极两侧的基板共面的两个浮动栅极。