公开(公告)号：US08288231B1

公开(公告)日：2012-10-16

申请号：US13212209

申请日：2011-08-18

Applicant: Wei-Ming Liao ,  Ming-Cheng Chang

Inventor： Wei-Ming Liao ,  Ming-Cheng Chang

IPC: H01L21/336

CPC classification number: H01L27/10876 ,  H01L21/28114 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/66621 ,  H01L29/66628

Abstract: A method of fabricating a recessed channel access transistor device is provided. First, a semiconductor substrate having thereon a recess etched into a major surface is provided. A gate dielectric layer is then formed on interior surface of the recess. A recessed gate electrode is then formed in and on the recess. The recessed gate electrode comprises a recessed gate portion that is inlaid into the recess and under the major surface, and an upper gate portion above the major surface. An exposed sidewall of the recessed gate electrode is isotropically etched to thereby form a trimmed neck portion having a width that is smaller than that of the recessed gate portion. An exposed sidewall of the trimmed neck portion is then oxidized.

Abstract translation: 提供一种制造凹槽通道存取晶体管器件的方法。 首先，提供其上具有蚀刻成主表面的凹部的半导体衬底。 然后在凹部的内表面上形成栅极电介质层。 然后在凹部中和凹部上形成凹陷栅电极。 凹陷栅电极包括凹入的栅极部分，其嵌入凹部中并在主表面下方，以及在上表面上方的上栅极部分。 凹入栅电极的暴露的侧壁被各向同性地蚀刻，从而形成宽度小于凹入栅极部分的宽度的修整颈部。 然后将经修整的颈部的暴露的侧壁氧化。

公开(公告)号：US07985998B2

公开(公告)日：2011-07-26

申请号：US12177756

申请日：2008-07-22

Applicant: Shian-Jyh Lin ,  Ming-Cheng Chang ,  Neng Tai Shih ,  Hung-Chang Liao

Inventor： Shian-Jyh Lin ,  Ming-Cheng Chang ,  Neng Tai Shih ,  Hung-Chang Liao

IPC: H01L27/108

CPC classification number: H01L27/10841 ,  H01L27/10864 ,  H01L27/10867 ,  H01L28/55

Abstract: A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper portion includes a conductive layer formed therein. The lower portion includes a trench capacitor formed therein. The gate dielectric layer is located between the semiconductor substrate and the conductive layer. The substrate channel structure with openings, adjacent to the trench, is electrically connected to the semiconductor substrate via the openings.

Abstract translation: 公开了一种沟槽型半导体器件结构。 该结构包括半导体衬底，栅介质层和衬底沟道结构。 半导体衬底包括具有上部和下部的沟槽。 上部包括形成在其中的导电层。 下部包括形成在其中的沟槽电容器。 栅介质层位于半导体衬底和导电层之间。 具有与沟槽相邻的开口的衬底沟道结构经由开口电连接到半导体衬底。

公开(公告)号：US20100202468A1

公开(公告)日：2010-08-12

申请号：US12635007

申请日：2009-12-10

Applicant: Ming-Cheng Chang

Inventor： Ming-Cheng Chang

IPC: H04L12/56

CPC classification number: H03M7/30 ,  G06F13/385 ,  G06F2213/3804

Abstract: Provided is a bridge coupled between an external host and an external storage device. The bridge includes a first interface, an encoder, a memory device, a decoder and a second interface. The first interface is coupled to the external host and receives a first data from an external host. The encoder is coupled to the first interface and compresses the first data by undistorted compression for producing a second data. The memory device is coupled to the encoder and temporally stores the second data produced by the encoder. The decoder is coupled to the memory device and decompresses the second data stored in the memory device for producing a third data. The third data and the first data are substantially the same. The second interface is coupled between the decoder and the external storage device and outputs the third data transmitted from the decoder to the external storage device.

Abstract translation: 提供了耦合在外部主机和外部存储设备之间的桥。 该桥包括第一接口，编码器，存储器件，解码器和第二接口。 第一个接口耦合到外部主机，并从外部主机接收第一个数据。 编码器耦合到第一接口并且通过未失真压缩来压缩第一数据以产生第二数据。 存储器件耦合到编码器并在时间上存储由编码器产生的第二数据。 解码器耦合到存储器件并解压存储在存储器件中的第二数据，以产生第三数据。 第三数据和第一数据基本相同。 第二接口耦合在解码器和外部存储装置之间，并将从解码器发送的第三数据输出到外部存储装置。

公开(公告)号：US20090166702A1

公开(公告)日：2009-07-02

申请号：US12177756

申请日：2008-07-22

Applicant: Shian-Jyh LIN ,  Ming-Cheng Chang ,  Neng Tai Shih ,  Hung-Chang Liao

Inventor： Shian-Jyh LIN ,  Ming-Cheng Chang ,  Neng Tai Shih ,  Hung-Chang Liao

IPC: H01L27/108

CPC classification number: H01L27/10841 ,  H01L27/10864 ,  H01L27/10867 ,  H01L28/55

Abstract: A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper portion includes a conductive layer formed therein. The lower portion includes a trench capacitor formed therein. The gate dielectric layer is located between the semiconductor substrate and the conductive layer. The substrate channel structure with openings, adjacent to the trench, is electrically connected to the semiconductor substrate via the openings.

Abstract translation: 公开了一种沟槽型半导体器件结构。 该结构包括半导体衬底，栅介质层和衬底沟道结构。 半导体衬底包括具有上部和下部的沟槽。 上部包括形成在其中的导电层。 下部包括形成在其中的沟槽电容器。 栅极电介质层位于半导体衬底和导电层之间。 具有与沟槽相邻的开口的衬底沟道结构经由开口电连接到半导体衬底。

公开(公告)号：US20090085089A1

公开(公告)日：2009-04-02

申请号：US12099168

申请日：2008-04-08

Applicant: Ming-Cheng Chang ,  Wei-Ming Liao ,  Jer-Chyi Wang ,  Yi-Feng Chang

Inventor： Ming-Cheng Chang ,  Wei-Ming Liao ,  Jer-Chyi Wang ,  Yi-Feng Chang

IPC: H01L29/788

CPC classification number: H01L29/7887 ,  H01L21/28273 ,  H01L29/42336

Abstract: A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced.

Abstract translation: 闪存包括具有突起的基板，控制栅极，两个浮动栅极和介电层。 突出部从基板的顶面延伸。 控制栅极形成在基板的突起上并且延伸地覆盖突起的相对的侧壁。 浮动栅极分别形成在突起的顶部并且位于控制栅极的两个相对侧上。 电介质层夹在控制栅极和两个浮栅之中。 由于在闪速存储器中使用的弧形控制门，所以控制栅极的可控性增加并且存储单元窗口被增强。

公开(公告)号：US20090047764A1

公开(公告)日：2009-02-19

申请号：US11953076

申请日：2007-12-10

Applicant: Wei-Ming Liao ,  Ming-Cheng Chang ,  Chien-Chang Huang

Inventor： Wei-Ming Liao ,  Ming-Cheng Chang ,  Chien-Chang Huang

IPC: H01L21/336

CPC classification number: H01L27/11521

Abstract: A non-volatile memory having a gate structure and a source/drain region is provided. The gate structure is disposed on a substrate. The gate structure includes a pair of floating gates, tunneling dielectric layers, a control gate and an inter-gate dielectric layer. The floating gates are disposed on the substrate. Each tunneling dielectric layer is disposed between each floating gate and the substrate. The control gate is disposed on the substrate between the pair of the floating gates and covers a top surface and sidewalls of each floating gate. The inter-gate dielectric layer is disposed between the control gate and each of the floating gates, disposed between the control gate and each of the tunneling dielectric layers, and disposed between the control gate and the substrate. The source/drain region is disposed in the substrate at respective sides of the gate structure.

Abstract translation: 提供具有栅极结构和源极/漏极区域的非易失性存储器。 栅极结构设置在基板上。 栅极结构包括一对浮置栅极，隧道电介质层，控制栅极和栅极间介电层。 浮置栅极设置在基板上。 每个隧道介电层设置在每个浮动栅极和衬底之间。 控制栅极设置在一对浮置栅极之间的衬底上并且覆盖每个浮动栅极的顶表面和侧壁。 栅极间电介质层设置在控制栅极和每个浮置栅极之间，设置在控制栅极和每个隧道介电层之间，并且设置在控制栅极和衬底之间。 源极/漏极区域在栅极结构的相应侧设置在衬底中。

公开(公告)号：US20060272770A1

公开(公告)日：2006-12-07

申请号：US11505009

申请日：2006-08-16

Applicant: Mao-Kan Lee ,  Ming-Cheng Chang ,  Zhing-Hung Chen ,  Yung-Hsiang Chou

Inventor： Mao-Kan Lee ,  Ming-Cheng Chang ,  Zhing-Hung Chen ,  Yung-Hsiang Chou

IPC: B65C9/25 ,  B32B37/00

CPC classification number: D06N3/145 ,  B32B38/06 ,  B32B2375/00 ,  B32B2459/00 ,  D06N3/007 ,  D06N3/0097

Abstract: Disclosed is a method for making artificial leather with superficial texture. In the method, a substrate is coated, in a non-overall manner, with a wet polyurethane resin. After curing, there is provided a polyurethane resin coated on releasing paper. Thus, a semi-product is made. Texture of the releasing paper is transferred to a surface of the semi-product. Then, the semi-product with the texture on the surface is coated with a layer of a chemical. A machine is used to heat and flatten the surface of the semi-product. Finally, the semi-product is physically finished by forces so that the surface of the final product is formed with texture like that of real leather.

Abstract translation: 公开了一种制造具有表面质地的人造革的方法。 在该方法中，以非整体方式用湿聚氨酯树脂涂布基材。 固化后，提供涂布在脱模纸上的聚氨酯树脂。 因此，制成半成品。 将释放纸的纹理转移到半成品的表面。 然后，表面上具有纹理的半成品涂上一层化学品。 一台机器用于加热和平坦化半成品的表面。 最后，半成品由力量物理完成，使得最终产品的表面形成有真实皮革的质感。

公开(公告)号：US07056832B2

公开(公告)日：2006-06-06

申请号：US10622965

申请日：2003-07-18

Applicant: Ming-Cheng Chang ,  Yi-Nan Chen ,  Tse-Yao Huang

Inventor： Ming-Cheng Chang ,  Yi-Nan Chen ,  Tse-Yao Huang

IPC: H01L21/302

CPC classification number: H01L27/10864 ,  H01L27/10867

Abstract: A deep trench self-alignment process for an active area of a partial vertical cell. A semiconductor substrate with two deep trenches is provided. A deep trench capacitor is formed in each deep trench, and an isolating layer is formed thereon. Each trench is filled with a mask layer. A photoresist layer is formed on the semiconductor substrate between the deep trenches, and the photoresist layer partially covers the mask layer. The semiconductor substrate is etched lower than the isolating layer using the photoresist layer and the mask layer as masks. The photoresist layer and the mask layer are removed, such that the pillar semiconductor substrate between the deep trenches functions as an active area.

Abstract translation: 用于部分垂直单元的活动区域的深沟槽自对准过程。 提供具有两个深沟槽的半导体衬底。 在每个深沟槽中形成深沟槽电容器，并在其上形成隔离层。 每个沟槽填充有掩模层。 在深沟槽之间的半导体衬底上形成光致抗蚀剂层，并且光致抗蚀剂层部分地覆盖掩模层。 使用光致抗蚀剂层和掩模层作为掩模，将半导体衬底蚀刻成比隔离层低。 去除光致抗蚀剂层和掩模层，使得深沟槽之间的柱状半导体衬底用作有效区域。

公开(公告)号：US20060109574A1

公开(公告)日：2006-05-25

申请号：US10994628

申请日：2004-11-22

Applicant: Ming-Cheng Chang

Inventor： Ming-Cheng Chang

IPC: G02B5/08

CPC classification number: F21V7/0008 ,  F21S10/06 ,  F21V14/04 ,  F21V17/02 ,  F21W2131/406

Abstract: A reflective mechanism includes a base fixed on a support member of a stage lamp, a bracket fixed on the base, a mirror frame, and a reflective mirror mounted on the mirror frame. A hollow shaft rotatably extends through an axial hole of the base and includes a fork on an end thereof. The hollow shaft is driven by a first motor mounted on the base to turn about a longitudinal axis of the hollow shaft. The mirror frame includes a pivotal portion pivotally mounted to the fork of the hollow shaft. The pivotal portion of the mirror frame is driven by a second motor to pivot through transmission by an endless cord that extends through the hollow shaft without interfering with rotation of the hollow shaft.

Abstract translation: 反射机构包括固定在舞台灯的支撑构件上的基座，固定在基座上的支架，反射镜框架和安装在镜框上的反射镜。 空心轴可旋转地延伸穿过基座的轴向孔并且在其一端包括叉。 空心轴由安装在基座上的第一马达驱动，以围绕中空轴的纵向轴线转动。 镜框包括枢转地安装到中空轴的叉的枢转部分。 反射镜框架的枢转部分由第二电动机驱动，以通过传播通过延伸穿过中空轴的环形绳索枢转，而不会妨碍空心轴的旋转。

公开(公告)号：US06919245B2

公开(公告)日：2005-07-19

申请号：US10972505

申请日：2004-10-25

Applicant: Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

Inventor： Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/1087 ,  H01L27/10832 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66181

Abstract: A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.

Abstract translation: 用于布置深沟槽和有源区域的动态随机存取存储器（DRAM）单元布局及其制造方法。 有源区域包括两个垂直晶体管，一个常见的位线触点和两个深沟槽。 第一垂直晶体管形成在第一深沟槽与第一栅极导电线部分重叠的区域上。 第二垂直晶体管形成在第二深沟槽与第二栅极导电线部分重叠的区域上。