公开(公告)号：US20180114782A1

公开(公告)日：2018-04-26

申请号：US15717953

申请日：2017-09-28

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu ,  Yuan-Fu Lan ,  Hsien-Wen Hsu

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/49 ,  H01L21/56 ,  H01L25/00

Abstract: A manufacturing method of a package-on package structure including at least the following steps is provided. A die is bonded on a first circuit carrier. A spacer is disposed on the die. The spacer and the first circuit carrier are connected through a plurality of conductive wires. An encapsulant is formed to encapsulate the die, the spacer and the conductive wires. A thickness of the encapsulant is reduced until at least a portion of each of the conductive wires is removed to form a first package structure. A second package structure is stacked on the first package structure. The second package structure is electrically connected to the conductive wires.

公开(公告)号：US20180114704A1

公开(公告)日：2018-04-26

申请号：US15782862

申请日：2017-10-13

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4889 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.

公开(公告)号：US09899287B2

公开(公告)日：2018-02-20

申请号：US15469594

申请日：2017-03-27

Applicant: Powertech Technology Inc.

Inventor： Ting-Feng Su ,  Chia-Jen Chou

IPC: H01L23/28 ,  H01L23/52 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/20 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/351

Abstract: A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. The at least one circuit layer is disposed on a surface of the chip and a surface of the molding compound coplanar to the surface of the chip. The at least one circuit layer includes a plurality of traces. Each of the traces includes a first portion and a second portion. The first portion is located at an edge region of a projection of the chip onto the dielectric layer. A width of the first portion is larger than a width of the second portion. The at least one dielectric layer is disposed at a side of the at least one circuit layer.

公开(公告)号：US20180019235A1

公开(公告)日：2018-01-18

申请号：US15393264

申请日：2016-12-29

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Wen-Jeng Fan

IPC: H01L25/00 ,  H01L21/50 ,  H01L25/10

CPC classification number: H01L25/50 ,  H01L21/50 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014

Abstract: A first semiconductor package of a POP structure has a first body and a plurality of first solder balls. A second semiconductor package of the POP structure has a second body and a plurality of second solder balls. A stand-off mechanism is utilized to maintain a minimum gap between the first body and the second body while a reflow soldering process is performed. By performing the reflow soldering process, the first solder balls and the second solder balls are heated and engaging with one another so as to solder the first solder balls and the second solder balls to form a plurality of interposer solder balls. Each interposer solder ball has a height substantially equal to the minimum gap and a cross sectional width less than a pitch between two adjacent interposer solder balls. Thereby, the POP structure would be a fine pitch package.

公开(公告)号：US20170372981A1

公开(公告)日：2017-12-28

申请号：US15469594

申请日：2017-03-27

Applicant: Powertech Technology Inc.

Inventor： Ting-Feng Su ,  Chia-Jen Chou

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/20 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/351

Abstract: A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. The at least one circuit layer is disposed on a surface of the chip and a surface of the molding compound coplanar to the surface of the chip. The at least one circuit layer includes a plurality of traces. Each of the traces includes a first portion and a second portion. The first portion is located at an edge region of a projection of the chip onto the dielectric layer. A width of the first portion is larger than a width of the second portion. The at least one dielectric layer is disposed at a side of the at least one circuit layer.

公开(公告)号：US09837385B1

公开(公告)日：2017-12-05

申请号：US15461453

申请日：2017-03-16

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Wen-Jeng Fan

IPC: H01L23/34 ,  H01L21/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3142 ,  H01L24/02 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2225/06506 ,  H01L2225/06513

Abstract: A package includes a chip, a wire, a mold layer and a redistribution layer. The chip includes a conductive pad. The wire is bonded to the conductive pad of the chip. The mold layer surrounds the first chip and the wire. The redistribution layer is disposed on the mold layer and contacts an exposed portion of the wire.

公开(公告)号：US20170338128A1

公开(公告)日：2017-11-23

申请号：US15585160

申请日：2017-05-02

Applicant: Powertech Technology Inc.

Inventor： Jen-I Huang ,  Ching-Yang Chen

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/538 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A manufacturing method of a package structure is provided. The method includes the following steps. A redistribution circuit layer is formed on a first carrier. A die is disposed on the redistribution circuit layer. An encapsulant is formed to encapsulate the die. The first carrier is removed to expose a surface of the redistribution circuit layer. A plurality of recesses are formed on the surface of the redistribution circuit layer. A plurality of conductive terminals are formed corresponding to the recesses on the redistribution circuit layer. Another manufacturing method of a package structure is also provided.

公开(公告)号：US09825005B2

公开(公告)日：2017-11-21

申请号：US14960962

申请日：2015-12-07

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Yun-Hsin Yeh ,  Hung-Hsin Hsu

IPC: H01L25/04 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/683 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2924/1511 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/1815

Abstract: Disclosed is a semiconductor package with Pillar-Top-Interconnection (PTI) configuration, comprising a redistribution layer (RDL) formed on a carrier plane, a plurality of metal pillars disposed on the RDL, a chip bonded onto the RDL, and a molding core. The molding core is formed on the carrier plane and has a bottom surface defined by the carrier plane so that the RDL is embedded inside the molding core. The package thickness of the molding core is greater than the chip-bonding height of the chip so that the chip is completely embedded inside the molding core. The metal pillars are encapsulated at the peripheries of the molding core with a plurality of pillar top portions exposed from the molding core. The exposed pillar top portions are reentrant from a top surface of the molding core and uneven. Accordingly, it realizes the effects of ultra-thin and smaller footprint POP stacked assembly with fine pitch vertically electrical connections in POP structure. Also, it is possible to achieve zero spacing between POP stacked assembly.

公开(公告)号：US20170309597A1

公开(公告)日：2017-10-26

申请号：US15491982

申请日：2017-04-20

Applicant: Powertech Technology Inc.

Inventor： Yong-Cheng Chuang ,  Kuo-Ting Lin ,  Li-Chih Fang ,  Chia-Jen Chou

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/97 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0237 ,  H01L2224/02373 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

Abstract: A manufacturing method of a package structure includes at least the following steps. At least one first die is disposed over a carrier. The first die is encapsulated using a first encapsulant. The first encapsulant exposes part of the first die. A redistribution layer (RDL) is formed over the first encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first surface faces the first encapsulant. The first encapsulant and the first die are separated from the carrier. A plurality of second dies are disposed on the second surface of the RDL. The second dies are encapsulated using the second encapsulant. A plurality of conductive terminals are formed on the first surface of the RDL.

公开(公告)号：US20170256471A1

公开(公告)日：2017-09-07

申请号：US15432932

申请日：2017-02-15

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Li-Chih Fang ,  Chia-Chang Chang ,  Hung-Hsin Hsu ,  Wen-Hsiung Chang ,  Kee-Wei Chung ,  Chia-Wen Lien

IPC: H01L23/31 ,  H01L23/00 ,  H01L27/146 ,  H01L21/56 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13027 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/0132 ,  H01L2924/15311

Abstract: A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.