公开(公告)号：US09887148B1

公开(公告)日：2018-02-06

申请号：US15437444

申请日：2017-02-21

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Jen-I Huang ,  Ching-Yang Chen

IPC: H01L23/04 ,  H01L23/485 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/485 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2924/15313 ,  H01L2924/1533

Abstract: A fan-out semiconductor package includes a layer of adhesive covering a temporary carrier, a first redistribution layer disposed on the layer of adhesive, the first redistribution layer including a first metal layer having recessed areas. Metal pillars are plated to a first group of the recessed areas in the first metal layer. A semiconductor chip next is bonded to a second group of the recessed areas and a molding compound covers the semiconductor chip. The molding compound is then ground to expose tops of the metal pillars. A second redistribution layer including a second passivation layer adhering to the molding compound and a second metal layer covering openings exposing the tops of the metal pillars are then added.

公开(公告)号：US20170338128A1

公开(公告)日：2017-11-23

申请号：US15585160

申请日：2017-05-02

Applicant: Powertech Technology Inc.

Inventor： Jen-I Huang ,  Ching-Yang Chen

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/538 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A manufacturing method of a package structure is provided. The method includes the following steps. A redistribution circuit layer is formed on a first carrier. A die is disposed on the redistribution circuit layer. An encapsulant is formed to encapsulate the die. The first carrier is removed to expose a surface of the redistribution circuit layer. A plurality of recesses are formed on the surface of the redistribution circuit layer. A plurality of conductive terminals are formed corresponding to the recesses on the redistribution circuit layer. Another manufacturing method of a package structure is also provided.