公开(公告)号：US06808995B2

公开(公告)日：2004-10-26

申请号：US10361681

申请日：2003-02-11

Applicant: Hung-Sui Lin ,  Han Chao Lai ,  Tao Cheng Lu

Inventor： Hung-Sui Lin ,  Han Chao Lai ,  Tao Cheng Lu

IPC: H01L21336

CPC classification number: H01L29/78603 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66757 ,  H01L29/66772

Abstract: A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions to minimize the short-channel effects, a conductor layer disposed over the source region, shallow trench isolation, and drain region, wherein the conductor layer electrically connects the source and drain regions to serve as a channel region, a gate oxide disposed over the conductor layer, and a gate structure formed over the gate oxide.

Abstract translation: 一种晶体管器件，其包括至少两个晶体管，每个晶体管包括在源极和漏极区域之间形成并邻接的源区域，漏极区域和浅沟槽隔离，其中浅沟槽隔离将源极和漏极区域电隔离成 最小化短沟道效应，设置在源极区域上的导体层，浅沟槽隔离和漏极区域，其中导体层将源极和漏极区域电连接以用作沟道区域，设置在导体层上的栅极氧化物 ，以及形成在栅极氧化物上的栅极结构。

公开(公告)号：US06720614B2

公开(公告)日：2004-04-13

申请号：US10005270

申请日：2001-12-04

Applicant: Hung-Sui Lin ,  Nian-Kai Zous ,  Han-Chao Lai ,  Tao-Cheng Lu

Inventor： Hung-Sui Lin ,  Nian-Kai Zous ,  Han-Chao Lai ,  Tao-Cheng Lu

IPC: H01L29788

CPC classification number: G11C16/0475 ,  H01L29/7887 ,  H01L29/7923

Abstract: A method for operating a P-channel SONOS memory device that has a charge trapping layer located on a substrate, a gate electrode located on the trapping layer, two doped regions located in the substrate at each side of the charge trapping layer. The two doped regions are set to be a drain region and a source region. When a programming action is intended, the gate electrode and the drain region are applied with a first negative high-level bias, and the source region and the substrate are applied with a grounded voltage. When an erasing action is intended, the gate electrode is a second negative bias which is smaller than the first negative voltage in absolute value. In the mean time, the drain region is applied with the third negative bias and the substrate is applied with a grounded voltage. The third negative voltage is larger than the second negative bias in absolute value.

Abstract translation: 一种用于操作具有位于衬底上的电荷俘获层的P沟道SONOS存储器件的方法，位于俘获层上的栅电极，位于电荷俘获层每侧的衬底中的两个掺杂区。 两个掺杂区域被设置为漏极区域和源极区域。 当需要编程动作时，栅极电极和漏极区域被施加第一负的高电平偏置，并且源区域和衬底被施加接地电压。 当需要擦除动作时，栅电极是比绝对值中的第一负电压小的第二负偏压。 同时，漏极区域被施加第三负偏压，并且衬底被施加接地电压。 第三负电压大于绝对值中的第二负偏压。

公开(公告)号：US06713821B2

公开(公告)日：2004-03-30

申请号：US10155619

申请日：2002-05-24

Applicant: Tso-Hung Fan ,  Mu-Yi Liu ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

Inventor： Tso-Hung Fan ,  Mu-Yi Liu ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC: H01L31062

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: A mask ROM device is described. The mask ROM device includes a substrate, a gate, a double diffused source/drain region that comprises a first doped region and a second doped region, a channel region, a coding region, a dielectric layer and a word line. The gate is disposed on the substrate. The double diffused source/drain region is positioned beside the sides of the gate in the substrate, wherein the second doped region is located at the periphery of the first doped region in the substrate. The channel region is located between the double diffused source/drain region in the substrate. The coding region is disposed in the substrate at the intersection between the sides of the channel region and the double diffused source/drain region. The dielectric layer is disposed above the double diffused source/drain region, while the word line is disposed above the dielectric layer and the gate.

Abstract translation: 描述掩模ROM设备。 掩模ROM器件包括衬底，栅极，包括第一掺杂区域和第二掺杂区域的双扩散源极/漏极区域，沟道区域，编码区域，电介质层和字线。 栅极设置在基板上。 双扩散源极/漏极区域位于衬底中的栅极的侧面旁边，其中第二掺杂区域位于衬底中的第一掺杂区域的外围。 沟道区位于衬底中的双扩散源极/漏极区之间。 编码区域设置在沟道区域和双扩散源极/漏极区域的相交处的衬底中。 电介质层设置在双扩散源极/漏极区域的上方，而字线设置在电介质层和栅极之上。

公开(公告)号：US06683352B2

公开(公告)日：2004-01-27

申请号：US10078314

申请日：2002-02-15

Applicant: Tsung-Hsuan Hsieh ,  Yao-Wen Chang ,  Tao-Cheng Lu

Inventor： Tsung-Hsuan Hsieh ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H01L2976

CPC classification number: H01L21/823425 ,  H01L21/823443 ,  H01L29/4238 ,  H01L29/665

Abstract: A metal oxide semiconductor field effect transistor structure is disclosed. A p-shape gate, disposed over a semiconductor substrate. A gate dielectric layer is disposed in between the p-shape gate and the semiconductor substrate. A drain region is disposed within the semiconductor substrate, wherein the drain region is surrounded by the p-shape gate. A source region is disposed within the semiconductor substrate, wherein the source region surrounds the p-shape gate. A silicide structure is disposed on the source/drain regions and the p-shape gate.

Abstract translation: 公开了一种金属氧化物半导体场效应晶体管结构。 p型栅极，设置在半导体衬底上。 栅极电介质层设置在p型栅极和半导体衬底之间。 漏极区域设置在半导体衬底内，其中漏极区域被p型栅极包围。 源极区域设置在半导体衬底内，其中源极区域围绕p形栅极。 在源极/漏极区域和p形栅极上设置硅化物结构。

公开(公告)号：US06661273B1

公开(公告)日：2003-12-09

申请号：US10225160

申请日：2002-08-22

Applicant: Chun-Hsiang Lai ,  Meng-Huang Liu ,  Shin Su ,  Tao-Cheng Lu

Inventor： Chun-Hsiang Lai ,  Meng-Huang Liu ,  Shin Su ,  Tao-Cheng Lu

IPC: H03K508

CPC classification number: H01L27/0277 ,  H03K5/08

Abstract: A substrate pump circuit and method for I/O ESD protection including NMOS fingers connected to the interconnection between an I/O pad and an internal circuit comprises a MOS device connected to the interconnection between the I/O pad and the internal circuit and the substrate under the control of a switch to turn it on to conduct a pumping current through the substrate resistor when the I/O pad is under ESD stress, so as to pull up the potential of the substrate adjacent to the NMOS fingers, resulting in the reduction of the triggering voltage of the NMOS fingers.

Abstract translation: 用于I / O ESD保护的衬底泵电路和方法，包括连接到I / O焊盘和内部电路之间的互连的NMOS指状包括连接到I / O焊盘和内部电路与衬底之间的互连的MOS器件 在I / O焊盘处于ESD应力下时，在开关控制下将其导通以通过衬底电阻器进行泵浦电流，从而上升与NMOS指状物相邻的衬底的电位，从而减少 的NMOS手指的触发电压。

公开(公告)号：US06643176B1

公开(公告)日：2003-11-04

申请号：US10064917

申请日：2002-08-29

Applicant: Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

Inventor： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC: G11C1606

CPC classification number: G11C16/30 ,  G11C8/08 ,  G11C11/5642 ,  G11C2211/5634

Abstract: A reference current generation circuit for the multiple bit flash memory provided by the present invention applies the same boosted word-line voltage to a voltage dividing circuit of the different reference current generation unit, so as to generate a gate voltage for the different reference current generation unit's reference cell to obtain the reference currents with different levels that are needed. Therefore, it effectively solves the problem of the reference currents having different drifts along with the variance of the temperature and the power voltage Vcc.

Abstract translation: 由本发明提供的用于多位闪存的参考电流产生电路将相同的升压字线电压施加到不同参考电流产生单元的分压电路，以产生用于不同参考电流产生的栅极电压 单位的参考单元，以获得所需水平不同的参考电流。 因此，它有效地解决了具有不同漂移的参考电流以及温度变化和电源电压Vcc的问题。

公开(公告)号：US06590266B1

公开(公告)日：2003-07-08

申请号：US10064906

申请日：2002-08-28

Applicant: Mu-Yi Liu ,  Tso-Hung Fan ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

Inventor： Mu-Yi Liu ,  Tso-Hung Fan ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC: H01L2994

CPC classification number: H01L27/11266 ,  H01L27/112

Abstract: A 2-bit mask ROM device and a fabrication method thereof are described. The 2-bit mask ROM device includes a substrate; a gate structure, disposed on a part of the substrate; a 2-bit code region, configured in the substrate beside both sides of the gate structure; at least one spacer, disposed on both sides of the gate structure; a buried drain region, configured in the substrate beside both sides of the spacer; a doped region, configured in the substrate between the buried drain region and the 2-bit code region, wherein the dopant type of the doped region is different from that for the 2-bit code region and the dopant concentration in the doped region is higher than that in the 2-bit code region; an insulation layer, disposed above the buried drain region; and a word line disposed on the gate structures along a same row.

Abstract translation: 描述2位掩模ROM器件及其制造方法。 2位掩模ROM器件包括衬底; 栅极结构，设置在所述衬底的一部分上; 2位代码区，配置在栅极结构的两侧旁边的基板中; 设置在所述栅极结构的两侧的至少一个间隔物; 掩埋漏极区域，被构造在所述衬底旁边的所述间隔物的两侧; 掺杂区域，配置在掩埋漏极区域和2位码区域之间的衬底中，其中掺杂区域的掺杂剂类型与2位码区域的掺杂区域不同，并且掺杂区域中的掺杂剂浓度更高 比在2位代码区域; 绝缘层，设置在所述掩埋漏极区域的上方; 以及沿同一行设置在栅极结构上的字线。

公开(公告)号：US06576934B2

公开(公告)日：2003-06-10

申请号：US10278135

申请日：2002-10-22

Applicant: Tao Cheng ,  Jian-Hsing Lee

Inventor： Tao Cheng ,  Jian-Hsing Lee

IPC: H01L2974

CPC classification number: H01L27/0262

Abstract: An embedded SCR in conjunction with a Gated-NMOS is created for protecting a chip input or output pad from ESD, by inserting a p+ diffusion and the n-well in the drain side and a part of the drain to forms a low-trigger, high efficiency SCR. The device layout is such that the drain connection is tightly tied together at the p+ diffusion and the n+ drain making that connection very short and, thereby, preventing latch-up. The parasitic SCR is contained entirely within the n+ diffusion (the source of the grounded gate NMOS transistor) at either side of the structure and, therefore, called an embedded SCR. For a 12 volt I/O device each of two n+ drains is placed in its own n-type doped drain (ndd) area straddling halfway the n-well. The structure is repeated as required and a p+ diffusion is implanted at both perimeters and connected to the nearest n+ source and a reference voltage.

Abstract translation: 通过在漏极侧和漏极的一部分插入p +扩散和n阱，形成嵌入式SCR，与栅极NMOS相结合，用于保护芯片输入或输出焊盘免受ESD影响，形成低触发， 高效SCR。 器件布局使得漏极连接在p +扩散和n +漏极紧密连接在一起，使得该连接非常短，从而防止闩锁。 寄生SCR完全包含在结构两侧的n +扩散（接地栅极NMOS晶体管的源极）内，因此被称为嵌入式SCR。 对于12伏I / O设备，两个n +漏极中的每一个都放置在跨越n-阱一半的其自身的n型掺杂漏极（ndd）区域中。 根据需要重复该结构，并且在两个周边注入p +扩散并连接到最近的n +源和参考电压。

公开(公告)号：US06555844B1

公开(公告)日：2003-04-29

申请号：US10101930

申请日：2002-03-21

Applicant: Hung-Sui Lin ,  Han Chao Lai ,  Tao Cheng Lu

Inventor： Hung-Sui Lin ,  Han Chao Lai ,  Tao Cheng Lu

IPC: H01L31036

CPC classification number: H01L29/78603 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66757 ,  H01L29/66772

Abstract: A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions to minimize the short-channel effects, a conductor layer disposed over the source region, shallow trench isolation, and drain region, wherein the conductor layer electrically connects the source and drain regions to serve as a channel region, a gate oxide disposed over the conductor layer, and a gate structure formed over the gate oxide.

Abstract translation: 一种晶体管器件，其包括至少两个晶体管，每个晶体管包括在源极和漏极区域之间形成并邻接的源区域，漏极区域和浅沟槽隔离，其中浅沟槽隔离将源极和漏极区域电隔离成 最小化短沟道效应，设置在源极区域上的导体层，浅沟槽隔离和漏极区域，其中导体层将源极和漏极区域电连接以用作沟道区域，设置在导体层上的栅极氧化物 ，以及形成在栅极氧化物上的栅极结构。

公开(公告)号：US06549029B1

公开(公告)日：2003-04-15

申请号：US09990261

申请日：2001-11-20

Applicant: Tsung-Hsuan Hsieh ,  Yao-Wen Chang ,  Tao-Cheng Lu

Inventor： Tsung-Hsuan Hsieh ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: G01R3126

CPC classification number: G01R27/2605

Abstract: A circuit structure for measuring a capacitive load. The capacitive load is coupled between a first and a second nodes, and drains of a first PMOS and a first NMOS transistors are coupled to the first node, and drains of a second PMOS and a second NMOS transistors are coupled to the second node, and a pad is coupled to the second node. First, sources of the first and the second PMOS transistors and sources of the first and the second NMOS transistors are biased at a power source and a ground respectively. A non-synchronized voltage is applied to gates of the first and the second PMOS transistors and to gates of the first and the second NMOS transistors simultaneously. By grounding and floating the pad, a current flowing through the capacitive load is obtained to calculate the capacitance.

Abstract translation: 用于测量电容性负载的电路结构。 电容性负载耦合在第一和第二节点之间，并且第一PMOS和第一NMOS晶体管的漏极耦合到第一节点，并且第二PMOS和第二NMOS晶体管的漏极耦合到第二节点，并且 垫连接到第二节点。 首先，第一和第二PMOS晶体管的源极和第一和第二NMOS晶体管的源极分别偏置在电源和地。 非同步电压同时施加到第一和第二PMOS晶体管的栅极和第一和第二NMOS晶体管的栅极。 通过接地和浮动焊盘，获得流过电容性负载的电流来计算电容。