公开(公告)号：US20110063281A1

公开(公告)日：2011-03-17

申请号：US12603579

申请日：2009-10-21

Applicant: Chao-Ching Hsu ,  Wei-Cheng Lin ,  Yu-Chun Tsai

Inventor： Chao-Ching Hsu ,  Wei-Cheng Lin ,  Yu-Chun Tsai

IPC: G09G5/00

CPC classification number: G09G3/3648 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2300/0465 ,  G09G2310/0297 ,  G09G2320/0223

Abstract: A pixel array, a driving method thereof and a flat panel display using the same are provided. The pixel array includes a first, a second, a third, and a fourth scan lines. A plurality of pixels is disposed between the first and the second scan lines. A plurality of pixels is disposed between the third and the fourth scan lines. In a first frame period, a gate driving circuit sequentially provides a driving signal to the first, the second, the fourth and the third scan lines. In a second frame period, the gate driving circuit sequentially provides the driving signal to the second, the first, the third and the fourth scan lines.

Abstract translation: 提供像素阵列，其驱动方法和使用其的平板显示器。 像素阵列包括第一，第二，第三和第四扫描线。 多个像素设置在第一和第二扫描线之间。 多个像素设置在第三和第四扫描线之间。 在第一帧周期中，栅极驱动电路依次向第一，第二，第四和第三扫描线提供驱动信号。 在第二帧周期中，栅极驱动电路依次向第二扫描线，第一扫描线，第三扫描线和第四扫描线提供驱动信号。

公开(公告)号：US07783373B2

公开(公告)日：2010-08-24

申请号：US11934241

申请日：2007-11-02

Applicant: Shin-Mu Tseng ,  Wei-Cheng Lin

Inventor： Shin-Mu Tseng ,  Wei-Cheng Lin

IPC: G06F19/00 ,  G06F11/30 ,  G01N37/00 ,  G05B23/02

CPC classification number: G05B19/4184 ,  G05B2219/31304 ,  G05B2219/45031 ,  Y02P90/10 ,  Y02P90/14

Abstract: A process debug method used to identify at least one excursive machine in a manufacturing process comprising the following steps: First, a series of validity identification data is collected, and the serial validity identification data is associated with its pathway to obtain a plurality of validity identification data sequences in corresponding to the machines. Subsequently, a sorting process is conducted to cluster the validity identification data sequence into several groups, and the clustered groups are ranked into a first order. The validity identification data sequences are subjected a continuity analysis to determine the continuity of the defects occurring in a particular machine. And the continuities of the machines involved in a particular group are ranked into a second order. Accordingly, the excursive machines causing the defective end products in the manufacturing process can be identified by the way of joining the second orders according to the first order.

Abstract translation: 一种用于在制造过程中识别至少一个偏移机器的过程调试方法，包括以下步骤：首先，收集一系列有效性识别数据，并且将串行有效性识别数据与其路径相关联以获得多个有效性标识 对应于机器的数据序列。 随后，执行排序处理以将有效性识别数据序列聚类成多个组，并且将聚类组排列成第一顺序。 对有效性识别数据序列进行连续性分析以确定在特定机器中发生的缺陷的连续性。 并且涉及特定组的机器的连续性被排列成二级。 因此，可以通过按照第一顺序连接第二顺序来识别导致制造过程中的有缺陷的最终产品的偏移机器。

公开(公告)号：US20100060361A1

公开(公告)日：2010-03-11

申请号：US12508126

申请日：2009-07-23

Applicant: Wei-Cheng Lin

Inventor： Wei-Cheng Lin

IPC: H03F3/04

CPC classification number: H03F3/45475 ,  H03F3/187 ,  H03F3/45991 ,  H03F2200/03 ,  H03F2200/375 ,  H03F2200/78 ,  H03F2203/45138 ,  H03F2203/45528 ,  H03F2203/45534 ,  H03F2203/45624

Abstract: The invention discloses a bias balancing circuit. The bias balancing circuit is used for balancing an output voltage outputted by an amplifier module. The amplifier module has a variable gain. The bias balancing circuit comprises a comparator and a voltage selector. The comparator is used for comparing the output voltage and a reference voltage, to generate a comparison signal. The voltage selector is used for generating a selected voltage according to the comparison signal. When the variable gain is changed to result in an offset from the output voltage to the reference voltage, the bias balancing circuit is capable of balancing the output voltage toward the reference voltage by the selected voltage.

Abstract translation: 本发明公开了一种偏置平衡电路。 偏置平衡电路用于平衡放大器模块输出的输出电压。 放大器模块具有可变增益。 偏置平衡电路包括比较器和电压选择器。 比较器用于比较输出电压和参考电压，以产生比较信号。 电压选择器用于根据比较信号产生所选择的电压。 当可变增益改变以导致从输出电压到参考电压的偏移时，偏置平衡电路能够通过所选择的电压平衡朝向参考电压的输出电压。

公开(公告)号：US20090102719A1

公开(公告)日：2009-04-23

申请号：US11984773

申请日：2007-11-21

Applicant: Wei-Cheng Lin

Inventor： Wei-Cheng Lin

IPC: G01S5/02

CPC classification number: G01S5/0252 ,  H04W4/029 ,  H04W4/33 ,  H04W64/00

Abstract: A local location-tracking system is installed in an indoor space, and comprises at least one tracked end, a plurality of second wireless signal transceivers and a local control end. The tracked end is movably located within the indoor space, and has at least one first wireless signal transceiver for sending a tracked signal. Each of the second wireless signal transceivers sends a detecting signal to the tracked end, the tracked end generates a response signal in accordance with the detecting signal, and the second wireless signal transceiver sends out a strength signal in accordance with a signal strength of the response signal. The local control end is applied to receive the strength signal and calculating a location coordinate of the tracked end in accordance with the signal strength.

Abstract translation: 本地位置跟踪系统安装在室内空间中，并且包括至少一个跟踪端，多个第二无线信号收发器和本地控制端。 跟踪端可移动地位于室内空间内，并且具有至少一个用于发送跟踪信号的第一无线信号收发器。 每个第二无线信号收发机向跟踪端发送检测信号，跟踪端根据检测信号产生响应信号，第二无线信号收发器根据响应的信号强度发出强度信号 信号。 应用本地控制端接收强度信号，并根据信号强度计算跟踪端的位置坐标。

公开(公告)号：US20090074154A1

公开(公告)日：2009-03-19

申请号：US12211264

申请日：2008-09-16

Applicant: Wei-Cheng Lin ,  Cheng-Ho Yu

Inventor： Wei-Cheng Lin ,  Cheng-Ho Yu

IPC: H04M1/24

CPC classification number: G01R31/002

Abstract: A measuring system comprises a pulse generator, an under test device, a variable resistor and a detecting control system. The pulse generator provides pulse signals with different voltage peaks to the under test device and the variable resistor. The variable resistor adjusts its resistance value according to a control signal. The detecting control system detects the voltage ringing ranges of the first terminal of the under test device at different resistance values. The detecting control system generates the control signal to adjust the resistance value of the variable resistor according to the voltage ringing ranges.

Abstract translation: 测量系统包括脉冲发生器，被测装置，可变电阻器和检测控制系统。 脉冲发生器向下测试装置和可变电阻器提供具有不同电压峰值的脉冲信号。 可变电阻根据控制信号调整其电阻值。 检测控制系统以不同的电阻值检测被测装置的第一端子的电压振铃范围。 检测控制系统产生控制信号，根据电压振铃范围调整可变电阻的电阻值。

公开(公告)号：US20090073135A1

公开(公告)日：2009-03-19

申请号：US12207264

申请日：2008-09-09

Applicant: WEI CHENG LIN ,  Kai Chieh Yang ,  Fu Yuan Hsueh ,  Ting Kuo Chang

Inventor： WEI CHENG LIN ,  Kai Chieh Yang ,  Fu Yuan Hsueh ,  Ting Kuo Chang

IPC: G06F3/041

CPC classification number: G06F3/044

Abstract: The present invention relates to a projecting capacitive touch sensing device, display panel, and image display system. The projecting capacitive touch sensing comprises an array of a plurality of sensing units, each sensing unit including: a first electrode made of a sensing material, at least one second electrode made of a sensing material and being disposed around the peripheral of the first electrode, at least one first sensing axis electrically connected to the first electrode, and at least one second sensing axis electrically connected to the second electrodes. The first electrode is quadrangle, while the second electrodes are triangular-shaped. The first electrode and the plurality of second electrodes are arranged to form a rectangular, and a non-sensing area is defined between the first electrode and the second electrodes.

Abstract translation: 本发明涉及投影电容式触摸感测装置，显示面板和图像显示系统。 投影电容触摸感测包括多个感测单元的阵列，每个感测单元包括：由感测材料制成的第一电极，由感测材料制成并且围绕第一电极的周边设置的至少一个第二电极， 电连接到第一电极的至少一个第一感测轴和电连接到第二电极的至少一个第二感测轴。 第一电极是四边形，而第二电极是三角形的。 第一电极和多个第二电极被布置成形成矩形，并且在第一电极和第二电极之间限定非感测区域。

公开(公告)号：US20080198054A1

公开(公告)日：2008-08-21

申请号：US12031736

申请日：2008-02-15

Applicant: Wei-Cheng Lin ,  Kai-Chieh Yang ,  Keiichi Sano ,  Fang-Hsing Wang ,  Ting-Yu Chang

Inventor： Wei-Cheng Lin ,  Kai-Chieh Yang ,  Keiichi Sano ,  Fang-Hsing Wang ,  Ting-Yu Chang

IPC: H03M1/66

CPC classification number: H03M1/804

Abstract: A digital to analog converter is provided comprising a charge sharing circuit, a discharging circuit and a voltage boosting circuit. The charge sharing circuit sequentially receives first to (N-1)th bits of serial digital signals. The charge sharing circuit shares and stores charges between a first capacitor and a second capacitor according to a charging voltage, a ground voltage, a first clock signal and serial data signals. The discharging circuit discharges the charge sharing circuit according to a reset signal. After the voltage boosting circuit receive the (N-1)th digital signal, the charge boosting circuit whether to boost a first terminal and a second terminal of the second capacitor or not based on an Nth digital signal. After the voltage boosting circuit receives the Nth serial digital signal, the charge sharing circuit outputs an analog signal from the second terminal of the second capacitor.

Abstract translation: 提供了一种数模转换器，包括电荷共享电路，放电电路和升压电路。 电荷共享电路顺序地接收串行数字信号的第一到第（N-1）位。 电荷共享电路根据充电电压，接地电压，第一时钟信号和串行数据信号共享和存储第一电容器和第二电容器之间的电荷。 放电电路根据复位信号对电荷共享电路进行放电。 在升压电路接收到第（N-1）个数字信号之后，充电提升电路是否基于第N个数字信号升压第二电容器的第一端子和第二端子。 在升压电路接收到第N串行数字信号之后，电荷共享电路从第二电容器的第二端子输出模拟信号。

公开(公告)号：US07342991B2

公开(公告)日：2008-03-11

申请号：US11385544

申请日：2006-03-20

Applicant: Chun-Ching Wei ,  Yang-En Wu ,  Wei-Cheng Lin

Inventor： Chun-Ching Wei ,  Yang-En Wu ,  Wei-Cheng Lin

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G11C19/00

Abstract: A shift register without a feedback signal of a post-stage shift register utilizing a latch mechanism and a clock signal to control the voltage of an output of the shift register is provided. The shift register reduces the transistor size and the circuit layout area. The shift register also improves the issue the overlapping between two adjacent shift registers to reduce the after-image of a liquid crystal display.

Abstract translation: 提供了没有使用锁存机构的后级移位寄存器的反馈信号的移位寄存器和用于控制移位寄存器的输出的电压的时钟信号。 移位寄存器可以减小晶体管尺寸和电路布局面积。 移位寄存器还改善了两个相邻移位寄存器之间的重叠以减少液晶显示器的后置图像的问题。

公开(公告)号：US20070188436A1

公开(公告)日：2007-08-16

申请号：US11456561

申请日：2006-07-10

Applicant: Chun-Ching Wei ,  Wei-Cheng Lin ,  Shih-Hsun Lo ,  Yang-En Wu

Inventor： Chun-Ching Wei ,  Wei-Cheng Lin ,  Shih-Hsun Lo ,  Yang-En Wu

IPC: G09G3/36

CPC classification number: G11C19/00 ,  G09G3/3677

Abstract: A shift register includes a signal generating circuit for generating an output signal at an output end of the shift register in response to a clock signal while the signal generating circuit is turned on, a driving circuit electrically coupled to the signal generating circuit for controlling the signal generating circuit in response to an input signal received from an input end of the shift register, a primary reset circuit electrically coupled to the signal generating circuit for turning off the signal generating circuit and resetting the output signal from the output end, and a feedback circuit electrically coupled to the output end and the major reset circuit for controlling the primary reset circuit in response to the output signal and the clock signal.

Abstract translation: 移位寄存器包括：信号发生电路，用于在信号产生电路导通时响应于时钟信号在移位寄存器的输出端产生输出信号;驱动电路，电耦合到信号发生电路，用于控制信号 响应于从所述移位寄存器的输入端接收到的输入信号产生电路;电耦合到所述信号发生电路的主复位电路，用于关闭所述信号发生电路并且从所述输出端复位所述输出信号;以及反馈电路 电耦合到输出端和主复位电路，用于响应于输出信号和时钟信号控制主复位电路。

公开(公告)号：US20070035505A1

公开(公告)日：2007-02-15

申请号：US11362213

申请日：2006-02-24

Applicant: Wei-Cheng Lin ,  Chun-Ching Wei ,  Yang-En Wu ,  Cheng-Liang Ma

Inventor： Wei-Cheng Lin ,  Chun-Ching Wei ,  Yang-En Wu ,  Cheng-Liang Ma

IPC: G09G3/36

CPC classification number: G11C19/28 ,  G09G3/3648 ,  G09G2310/0286 ,  G09G2320/0219

Abstract: A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the first transistor, an output and a first clock signal, and a pull-down module coupling to the output, output signals of pre-stage and post-stage shift register, a second and a third voltage level. When the second transistor turns on and the first clock signal is at high voltage level, the output is at a first voltage level. When the signal of post-stage shift register is at first voltage level, the output is at the third voltage level.

Abstract translation: 具有一系列级联移位寄存器的移位寄存器电路包括耦合到前级移位寄存器的输出信号的第一晶体管，耦合到第一晶体管的第二晶体管，输出和第一时钟信号以及下拉 模块耦合到输出，前级和后级移位寄存器的输出信号，第二和第三电压电平。 当第二晶体管导通并且第一时钟信号处于高电压电平时，输出处于第一电压电平。 当后级移位寄存器的信号处于第一电压电平时，输出处于第三电压电平。