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    STRESSED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING
    41.
    发明申请
    STRESSED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING 有权
    应力半导体器件及其制造方法

    公开(公告)号：US20120292639A1

    公开(公告)日：2012-11-22

    申请号：US13111732

    申请日：2011-05-19

    Applicant: Miao-Cheng Liao ,  Min Hao Hong ,  Hsiang Hsiang Ko ,  Kei-Wei Chen ,  Ying-Lang Wang

    Inventor： Miao-Cheng Liao ,  Min Hao Hong ,  Hsiang Hsiang Ko ,  Kei-Wei Chen ,  Ying-Lang Wang

    IPC: H01L29/06 ,  H01L29/24 ,  H01L21/762

    CPC classification number: H01L21/823807 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262

    Abstract: A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer.

    Abstract translation: 公开了一种制造半导体器件的半导体器件和方法。 用于制造半导体器件的示例性半导体器件和方法增强载流子迁移率。 该方法包括提供衬底并在衬底上形成电介质层。 该方法还包括在电介质层内形成第一沟槽，其中第一沟槽延伸穿过电介质层并且外延（epi）在第一沟槽内生长第一有源层，并用辐射能选择性地固化与第一沟槽相邻的介电层 活动层

    SEMICONDUCTOR DEVICE CONTACT STRUCTURES AND METHODS FOR MAKING THE SAME
    43.
    发明申请
    SEMICONDUCTOR DEVICE CONTACT STRUCTURES AND METHODS FOR MAKING THE SAME 有权
    半导体器件接触结构及其制造方法

    公开(公告)号：US20120235299A1

    公开(公告)日：2012-09-20

    申请号：US13049049

    申请日：2011-03-16

    Applicant: Shih Chieh CHANG ,  Chih-Chung CHANG ,  Kei-Wei CHEN ,  Ying-Lang WANG

    Inventor： Shih Chieh CHANG ,  Chih-Chung CHANG ,  Kei-Wei CHEN ,  Ying-Lang WANG

    IPC: H01L23/52 ,  H01L21/768

    CPC classification number: H01L23/53266 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor contact structure and method provide contact structures that extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings.

    Abstract translation: 半导体接触结构和方法提供延伸穿过电介质材料并提供与包括硅化物材料和非硅化物材料例如掺杂硅的多个不同下层材料的接触的接触结构。 接触结构包括使用多步电离金属等离子体（IMP）沉积操作形成的下复合层。 下部IMP膜以高AC偏压功率形成，随后以较低的AC偏压功率形成上部IMP膜。 复合层可以由钛形成。 在复合层上形成另一层作为衬垫，并且衬垫层可以有利地使用CVD形成，并且可以是TiN。 诸如钨或铜的导电插塞材料填充接触开口。

    Via/contact and damascene structures and manufacturing methods thereof
    44.
    发明授权
    Via/contact and damascene structures and manufacturing methods thereof 有权
    通孔/接触和镶嵌结构及其制造方法

    公开(公告)号：US08247322B2

    公开(公告)日：2012-08-21

    申请号：US11680981

    申请日：2007-03-01

    Applicant: Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

    Inventor： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

    IPC: H01L21/44

    CPC classification number: H01L21/76831 ,  H01L21/7684

    Abstract: A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.

    Abstract translation: 形成半导体结构的方法包括在衬底上形成电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 然后形成种子层和导电层，并且单次抛光操作去除种子层和导电层。

    Apparatuses for electrochemical deposition, conductive layer, and fabrication methods thereof
    46.
    发明授权
    Apparatuses for electrochemical deposition, conductive layer, and fabrication methods thereof 有权
    电化学沉积装置，导电层及其制造方法

    公开(公告)号：US07837841B2

    公开(公告)日：2010-11-23

    申请号：US11686504

    申请日：2007-03-15

    Applicant: Kei-Wei Chen ,  Mu-Han Cheng ,  Jian-Sin Tsai ,  Ying-Lang Wang

    Inventor： Kei-Wei Chen ,  Mu-Han Cheng ,  Jian-Sin Tsai ,  Ying-Lang Wang

    IPC: C25D5/00 ,  C25D5/18 ,  C25D17/00 ,  C25B15/00

    CPC classification number: C25D17/001 ,  C25D17/007 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76877 ,  Y10T428/16

    Abstract: Electrochemical plating (ECP) apparatuses with auxiliary cathodes to create uniform electric flux density. An ECP apparatus for electrochemical deposition includes an electrochemical cell with an electrolyte bath for electrochemically depositing a metal on a substrate. A main cathode and an anode are disposed in the electrolyte bath to provide a main electrical field. A substrate holder assembly holds a semiconductor wafer connecting the cathode. An auxiliary cathode is disposed outside the electrochemical cell to provide an auxiliary electrical field such that a flux line density at the center region of the substrate holder assembly substantially equals that at the circumference of the substrate holder assembly.

    Abstract translation: 具有辅助阴极的电化学电镀（ECP）装置，以产生均匀的电流密度。 用于电化学沉积的ECP设备包括具有用于在基底上电化学沉积金属的电解质浴的电化学电池。 主阴极和阳极设置在电解槽中以提供主电场。 衬底保持器组件保持连接阴极的半导体晶片。 辅助阴极设置在电化学电池外部以提供辅助电场，使得衬底保持器组件的中心区域处的磁通线密度基本上等于衬底保持器组件的圆周处的磁通密度。

    Forming Seed Layer in Nano-Trench Structure Using Net Deposition and Net Etch
    48.
    发明申请
    Forming Seed Layer in Nano-Trench Structure Using Net Deposition and Net Etch 审中-公开
    使用净沉积和净蚀刻在纳米沟槽结构中形成种子层

    公开(公告)号：US20090127097A1

    公开(公告)日：2009-05-21

    申请号：US11941435

    申请日：2007-11-16

    Applicant: Kei-Wei Chen ,  Shih-Ho Lin ,  Yu-Sheng Wang ,  Szu-An Wu ,  Ying-Lang Wang

    Inventor： Kei-Wei Chen ,  Shih-Ho Lin ,  Yu-Sheng Wang ,  Szu-An Wu ,  Ying-Lang Wang

    IPC: C23C14/00

    CPC classification number: C23C14/345 ,  C23C14/046 ,  H01L21/76862 ,  H01L21/76873

    Abstract: A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a net deposition step to form a seed layer having a portion in the opening, wherein the net deposition step comprises a first deposition and a first etching; performing a net etch step to the seed layer, wherein the net etch step comprises a first etching and a first deposition, wherein a portion of the seed layer remains after the net etch step; and growing a conductive material on the seed layer to fill a remaining portion of the opening.

    Abstract translation: 形成集成电路结构的方法包括形成电介质层; 在介电层中形成开口; 执行净沉积步骤以形成具有在开口中的一部分的种子层，其中所述净沉积步骤包括第一沉积和第一蚀刻; 对所述种子层进行净蚀刻步骤，其中所述净蚀刻步骤包括第一蚀刻和第一沉积，其中所述种子层的一部分在所述净蚀刻步骤之后保留; 以及在种子层上生长导电材料以填充开口的剩余部分。

    Copper plating of semiconductor devices using single intermediate low power immersion step
    49.
    发明授权
    Copper plating of semiconductor devices using single intermediate low power immersion step 有权
    采用单中级低功耗浸入式半导体器件镀铜

    公开(公告)号：US07312149B2

    公开(公告)日：2007-12-25

    申请号：US10840095

    申请日：2004-05-06

    Applicant: Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

    Inventor： Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

    IPC: H01L21/44

    CPC classification number: C25D7/123 ,  C25D3/02 ,  C25D5/10 ,  C25D5/18 ,  H01L21/2885

    Abstract: A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.

    Abstract translation: 在半导体器件上电镀金属层的方法包括一系列偏置操作，其包括第一电流密度的第一电镀步骤，随后是第二电流密度小于第一电流密度的第二浸入步骤，随后的电镀 从具有大于第一电流密度的第三电流密度的第三电镀步骤开始增加电流密度的步骤。 第二，低电流密度浸没步骤提高了电镀工艺的质量，并且产生完全填充诸如通孔和沟槽等开口的电镀膜，并避免了通孔和沟槽开口的底角上的中空通孔和拉回。 低电流密度第二浸入步骤产生电化学沉积工艺，其提供低接触电阻并因此减少器件故障。

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