公开(公告)号：US09673244B2

公开(公告)日：2017-06-06

申请号：US13415546

申请日：2012-03-08

Applicant: Shiu-Ko JangJian ,  Min Hao Hong ,  Kei-Wei Chen ,  Szu-An Wu

Inventor： Shiu-Ko JangJian ,  Min Hao Hong ,  Kei-Wei Chen ,  Szu-An Wu

IPC: H01L31/109 ,  H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/1464

Abstract: Image sensors comprising an isolation region according to embodiments are disclosed, as well as methods of forming the image sensors with isolation region. An embodiment is a structure comprising a semiconductor substrate, a photo element in the semiconductor substrate, and an isolation region in the semiconductor substrate. The isolation region is proximate the photo element and comprises a dielectric material and an epitaxial region. The epitaxial region is disposed between the semiconductor substrate and the dielectric material.

公开(公告)号：US09224773B2

公开(公告)日：2015-12-29

申请号：US13420279

申请日：2012-03-14

Applicant: Shih-Chieh Chang ,  Jian-Shin Tsai ,  Chih-Chang Huang ,  Ing-Ju Lee ,  Ching-Yao Sun ,  Jyun-Ru Wu ,  Ching-Che Huang ,  Szu-An Wu ,  Ying-Lang Wang

Inventor： Shih-Chieh Chang ,  Jian-Shin Tsai ,  Chih-Chang Huang ,  Ing-Ju Lee ,  Ching-Yao Sun ,  Jyun-Ru Wu ,  Ching-Che Huang ,  Szu-An Wu ,  Ying-Lang Wang

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14683 ,  H01L27/14685

Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.

Abstract translation: 一种器件包括具有正面和背面的半导体衬底。 光敏器件设置在半导体衬底的表面处，其中光敏器件被配置为从半导体衬底的背面接收光信号，并将光信号转换为电信号。 在半导体衬底的背面设有非晶态粘接层。 非晶态粘合层包括氮和金属的化合物。 金属屏蔽层设置在半导体衬底的背面并与非晶态粘合层接触。

公开(公告)号：US09219092B2

公开(公告)日：2015-12-22

申请号：US13396426

申请日：2012-02-14

Applicant: Shiu-Ko JangJian ,  Szu-An Wu ,  Sheng-Wen Chen

Inventor： Shiu-Ko JangJian ,  Szu-An Wu ,  Sheng-Wen Chen

IPC: H01L31/0232 ,  H01L27/146

CPC classification number: H01L27/1446 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689

Abstract: A device includes a semiconductor substrate, which has a front side and a backside. A photo-sensitive device is disposed on the front side of the semiconductor substrate. A first and a second grid line are parallel to each other, and are disposed on the backside of, and overlying, the semiconductor substrate. A stacked layer includes an adhesion layer, a metal layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines.

Abstract translation: 一种器件包括具有正面和背面的半导体衬底。 光敏装置设置在半导体基板的正面上。 第一和第二栅极线彼此平行，并且设置在半导体衬底的背面并且覆盖其上。 堆叠层包括粘合层，粘合层上的金属层和金属层上的高折射率层。 粘合层，金属层和高折射率层基本上共形，并且在第一和第二栅格线的顶表面和侧壁上延伸。

公开(公告)号：US08778602B2

公开(公告)日：2014-07-15

申请号：US12562248

申请日：2009-09-18

Applicant: Hung-Ting Pan ,  Jing-Huan Chen ,  Wei-Chung Ma ,  Hsin-Chun Chiang ,  Po-Chung Cheng ,  Szu-An Wu

Inventor： Hung-Ting Pan ,  Jing-Huan Chen ,  Wei-Chung Ma ,  Hsin-Chun Chiang ,  Po-Chung Cheng ,  Szu-An Wu

IPC: G03F7/30

CPC classification number: G03F7/30 ,  G03F7/38 ,  H01L21/0273

Abstract: A method of lithography patterning includes coating a resist layer on a substrate; performing an exposing process to the resist layer using a lithography tool with a numerical aperture tuned between about 0.5 and about 0.6; baking the resist layer; thereafter performing a first developing process to the resist layer for a first period of time; and performing a second developing process to the resist layer for a second period of time.

Abstract translation: 光刻图案的方法包括在基板上涂覆抗蚀剂层; 使用数值孔径调节在约0.5和约0.6之间的光刻工具对抗蚀剂层进行曝光处理; 烘烤抗蚀剂层; 然后对所述抗蚀剂层进行第一显影处理第一时间; 以及对所述抗蚀剂层进行第二显影处理第二时间段。

公开(公告)号：US08294202B2

公开(公告)日：2012-10-23

申请号：US12754761

申请日：2010-04-06

Applicant: Shiu-Ko Jangjian ,  Szu-An Wu ,  Sheng-Wen Chen

Inventor： Shiu-Ko Jangjian ,  Szu-An Wu ,  Sheng-Wen Chen

IPC: H01L21/02

CPC classification number: H01L29/66545 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66583 ,  H01L29/7833

Abstract: A semiconductor device structure, for improving the metal gate leakage within the semiconductor device. A structure for a metal gate electrode for a n-type Field Effect Transistor includes a capping layer; a first metal layer comprising Ti and Al over the capping layer; a metal oxide layer over the first metal layer; a barrier layer over the metal oxide layer; and a second metal layer over the barrier layer.

Abstract translation: 一种用于改善半导体器件内的金属栅极泄漏的半导体器件结构。 用于n型场效应晶体管的金属栅电极的结构包括封盖层; 在覆盖层上包含Ti和Al的第一金属层; 第一金属层上的金属氧化物层; 金属氧化物层上的阻挡层; 和阻挡层上的第二金属层。

公开(公告)号：US20060196526A1

公开(公告)日：2006-09-07

申请号：US11072114

申请日：2005-03-04

Applicant: Jun Wu ,  Dong-Xuan Lu ,  Shih-Chi Lin ,  Wen-Long Lee ,  Yi-An Jian ,  Guang-Cheng Wang ,  Shiu-Ko JangJian ,  Chyi-Tsong Ni ,  Szu-An Wu ,  Ying-Lang Wang

Inventor： Jun Wu ,  Dong-Xuan Lu ,  Shih-Chi Lin ,  Wen-Long Lee ,  Yi-An Jian ,  Guang-Cheng Wang ,  Shiu-Ko JangJian ,  Chyi-Tsong Ni ,  Szu-An Wu ,  Ying-Lang Wang

IPC: C23G1/00 ,  B08B7/00 ,  B08B3/00

CPC classification number: B08B1/04 ,  B08B3/02 ,  H01L21/67051

Abstract: A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is between 0.05 to 100 KPa.

公开(公告)号：US20060166458A1

公开(公告)日：2006-07-27

申请号：US11044814

申请日：2005-01-26

Applicant: Yi-Lung Cheng ,  Szu-An Wu ,  Yi-Lang Wang

Inventor： Yi-Lung Cheng ,  Szu-An Wu ,  Yi-Lang Wang

IPC: H01L21/76 ,  H01L21/461

CPC classification number: H01L21/31053 ,  H01L21/76224

Abstract: A shallow trench isolation (STI) structure for semiconductor devices is formed using a deposited silicon layer formed over a polish stop layer formed over an oxide formed on a substrate. The polish stop layer may be nitride. An opening is formed extending through the deposited silicon layer and the nitride and oxide layers and extending into the substrate. A deposited oxide is formed filling the opening and extending over the top surface of deposited silicon layer. A chemical mechanical polishing operation polishes the deposited silicon layer at a rate faster than the deposited oxide layer to produce an STI with a convex portion extending above the nitride layer. Dishing problems are avoided and the structure may be subsequently planarized.

Abstract translation: 用于半导体器件的浅沟槽隔离（STI）结构使用形成在形成在衬底上的氧化物上形成的抛光停止层上的沉积硅层形成。 抛光停止层可以是氮化物。 形成延伸穿过沉积的硅层和氮化物和氧化物层并延伸到衬底中的开口。 形成沉积氧化物，填充开口并在沉积的硅层的顶表面上延伸。 化学机械抛光操作以比沉积的氧化物层更快的速率抛光沉积的硅层，以产生具有在氮化物层上方延伸的凸部的STI。 避免了抛光问题，并且可以随后平面化该结构。

公开(公告)号：US06602560B2

公开(公告)日：2003-08-05

申请号：US10196850

申请日：2002-07-16

Applicant: Yi-Lung Cheng ,  Wen-Kung Cheng ,  Ming-Hwa Yoo ,  Szu-An Wu ,  Ying-Long Wang ,  Pei-Fen Chou

Inventor： Yi-Lung Cheng ,  Wen-Kung Cheng ,  Ming-Hwa Yoo ,  Szu-An Wu ,  Ying-Long Wang ,  Pei-Fen Chou

IPC: C23C1640

CPC classification number: C23C16/4405 ,  B08B7/0035

Abstract: A method of removing residual fluorine present in a HDP-CVD chamber which includes a high pressure seasoning process, a dry-cleaning process, and a low-pressure deposition process.

Abstract translation: 一种除去存在于HDP-CVD室中的残余氟的方法，其包括高压调味处理，干洗处理和低压沉积工艺。

公开(公告)号：US06585826B2

公开(公告)日：2003-07-01

申请号：US10000891

申请日：2001-11-02

Applicant: Yali Tai ,  Shih-Chi Lin ,  Wen-Long Lee ,  Francis Wang ,  Szu-An Wu ,  Hsi-Kuei Cheng ,  Ying-Lang Wang

Inventor： Yali Tai ,  Shih-Chi Lin ,  Wen-Long Lee ,  Francis Wang ,  Szu-An Wu ,  Hsi-Kuei Cheng ,  Ying-Lang Wang

IPC: C23G102

CPC classification number: H01L21/02063 ,  B08B1/00 ,  B08B3/04 ,  B08B3/12 ,  C11D7/265 ,  C11D11/0047 ,  H01L21/02074 ,  H01L21/67046 ,  H01L21/67057 ,  H01L21/67086 ,  Y10S134/902

Abstract: A method of removing residual contamination including metal nitride particles from semiconductor wafer surfaces including the steps of: providing at least one semiconductor wafer with metal nitride particles adhering to the at least one semiconductor wafer surface thereto; subjecting the at least one semiconductor wafer to at least one mechanical brushing process while a cleaning solution including a carboxylic acid is supplied to at least one semiconductor wafer surface; and, subjecting the at least one semiconductor wafer to an a sonic cleaning process including the carboxylic acid cleaning solution.

Abstract translation: 一种从半导体晶片表面去除包括金属氮化物颗粒的残留污染的方法，包括以下步骤：向至少一个半导体晶片提供附着在至少一个半导体晶片表面上的金属氮化物颗粒; 使至少一个半导体晶片进行至少一个机械刷洗过程，同时将包含羧酸的清洁溶液供应到至少一个半导体晶片表面; 以及对所述至少一个半导体晶片进行包括所述羧酸清洁溶液的声波清洁处理。

公开(公告)号：US06358761B1

公开(公告)日：2002-03-19

申请号：US09396521

申请日：1999-09-15

Applicant: Hui-Ju Yoo ,  Szu-An Wu ,  Cheng-Kun Lin ,  Shiow-Jye Jenq

Inventor： Hui-Ju Yoo ,  Szu-An Wu ,  Cheng-Kun Lin ,  Shiow-Jye Jenq

IPC: H01L21265

CPC classification number: G01N27/041

Abstract: A method and means for detection of oxidizing contamination in acid etching baths employed to etch silicon oxide layers from silicon substrates employed in silicon integrated circuit microelectronics fabrications. There is provided a silicon substrate having within a doped region formed employing ion implantation. The silicon substrate is immersed within a buffered oxide etch (BOE) acid bath, wherein the presence of an oxidizing contaminant correlates with an increase in the resistance of the doped region upon the removal of any silicon oxide layer on the silicon surface.

Abstract translation: 用于检测酸蚀刻液中的氧化污染物的方法和装置，其用于从用于硅集成电路微电子学制造的硅衬底上蚀刻氧化硅层。 提供了在采用离子注入形成的掺杂区域内的硅衬底。 将硅衬底浸入缓冲氧化物蚀刻（BOE）酸浴中，其中氧化污染物的存在与去除硅表面上的任何氧化硅层时的掺杂区域的电阻的增加相关。