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公开(公告)号：US20150255047A1
公开(公告)日：2015-09-10
申请号：US14201421
申请日：2014-03-07
Applicant: Apple Inc.
Inventor： Peter F. Holland , Guy Cote , Mark P. Rygh
CPC classification number: G09G5/39 , G09G5/001 , G09G5/022 , G09G5/363 , G09G2340/02 , G09G2340/06 , G09G2340/10 , G09G2340/12 , G09G2360/121 , G09G2360/128 , G09G2360/16
Abstract: In an embodiment, a system includes a display processing unit configured to process a video sequence for a target display. In some embodiments, the display processing unit is configured to composite the frames from frames of the video sequence and one or more other image sources. The display processing unit may be configured to write the processed/composited frames to memory, and may also be configured to generate statistics over the frame data, where the generated statistics are usable to encode the frame in a video encoder. The display processing unit may be configured to write the generated statistics to memory, and the video encoder may be configured to read the statistics and the frames. The video encoder may be configured to encode the frame responsive to the statistics.
Abstract translation: 在一个实施例中，系统包括被配置为处理用于目标显示的视频序列的显示处理单元。 在一些实施例中，显示处理单元被配置为从视频序列的帧和一个或多个其它图像源合成帧。 显示处理单元可以被配置为将经处理/合成的帧写入存储器，并且还可以被配置为生成关于帧数据的统计信息，其中生成的统计信息可用于对视频编码器中的帧进行编码。 显示处理单元可以被配置为将生成的统计信息写入存储器，并且视频编码器可以被配置为读取统计信息和帧。 视频编码器可以被配置为响应于统计信息对帧进行编码。
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公开(公告)号：US08963938B2
公开(公告)日：2015-02-24
申请号：US13744637
申请日：2013-01-18
Applicant: Apple Inc.
Inventor： Peter F. Holland
Abstract: In an embodiment, a display pipe processes video data for visual display. The display pipe may read the video data from memory, and may employ QoS levels with the memory requests to ensure that enough data is provided to satisfy the real time display requirements. The display pipe may include a pixel buffer that stores pixels that are ready for display. Additionally, the display pipe may include one or more input buffers configured to store input video data to be processed and/or one or more output buffers configured to store processed data that is ready for blending into the final pixels for display. The display pipe determine a number of output equivalent pixels in the data in the input and output buffers, and may consider those pixels as well as the ready pixels in the pixel buffer in determining the QoS levels for requests.
Abstract translation: 在一个实施例中，显示管处理用于视觉显示的视频数据。 显示管道可以从存储器读取视频数据，并且可以使用具有存储器请求的QoS级别来确保提供足够的数据以满足实时显示要求。 显示管可以包括存储准备显示的像素的像素缓冲器。 此外，显示管道可以包括被配置为存储要处理的输入视频数据的一个或多个输入缓冲器和/或被配置为存储处理后的数据的一个或多个输出缓冲器，该处理后的数据准备好进行混合到最终的像素中进行显示。 显示管确定输入和输出缓冲器中的数据中的输出等效像素的数量，并且可以在确定请求的QoS等级时考虑像素缓冲器中的那些像素以及就绪像素。
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公开(公告)号：US20140333643A1
公开(公告)日：2014-11-13
申请号：US13889816
申请日：2013-05-08
Applicant: APPLE INC.
Inventor： Albert C. Kuo , Peter F. Holland
IPC: G06T1/60
CPC classification number: G06T1/60 , G09G5/001 , G09G2360/12
Abstract: A system and method for efficiently scheduling memory access requests from a display controller pipeline. The display controller monitors the amount of data in the line buffers in the internal pixel-processing pipelines. The display controller waits until the amount of data in a given line buffer has fallen below an amount equal to the pixel width of the region being rendered by the internal pixel-processing pipeline before issuing memory requests to the memory controller. When the memory controller is not processing received memory requests, the memory controller transitions to a low-power state.
Abstract translation: 一种用于从显示控制器管线有效地调度存储器访问请求的系统和方法。 显示控制器监视内部像素处理流水线中的行缓冲器中的数据量。 在向存储器控制器发出存储器请求之前，显示控制器等待直到给定行缓冲器中的数据量已经下降到等于由内部像素处理流水线呈现的区域的像素宽度的量的量。 当存储器控制器不处理接收到的存储器请求时，存储器控制器转换到低功率状态。
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公开(公告)号：US20140232732A1
公开(公告)日：2014-08-21
申请号：US14263424
申请日：2014-04-28
Applicant: Apple Inc.
Inventor： Joseph P. Bratt , Peter F. Holland , Shing Horng Choo , Timothy J. Millet
IPC: G06T1/60
CPC classification number: G06T1/60 , G09G5/14 , G09G5/363 , G09G2340/10 , G09G2360/12 , G09G2360/127
Abstract: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.
Abstract translation: 图形系统可以包括用于处理当前显示帧的一个或多个处理单元，每个处理单元包括用于存储用于处理当前显示帧的参数设置的多个参数寄存器。 图形系统中的参数缓冲器可以存储帧分组，每个帧分组包含对应于要用于至少一个显示帧的参数设置的信息。 耦合到缓冲器和一个或多个处理单元的控制电路可以从参数缓冲器检索和处理顶部帧分组，以根据顶部帧分组的内容更新一个或多个参数寄存器。 控制电路可以发出DMA请求，用从系统存储器传送的帧分组填充参数缓冲器，其中帧分组可以由在中央处理单元上执行的应用（或软件）写入。
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公开(公告)号：US20250068229A1
公开(公告)日：2025-02-27
申请号：US18908018
申请日：2024-10-07
Applicant: Apple Inc.
Inventor： Ramana V. Rachakonda , Rohit K. Gupta , Brad W. Simeral , Peter F. Holland
IPC: G06F1/3287 , G06F1/3228 , H04B17/318
Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.
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Patent Agency Ranking
公开(公告)号：US20240094797A1
公开(公告)日：2024-03-21
申请号：US18476547
申请日：2023-09-28
Applicant: Apple Inc.
Inventor： Ramana V. Rachakonda , Rohit K. Gupta , Brad W. Simeral , Peter F. Holland
IPC: G06F1/3287 , G06F1/3228
CPC classification number: G06F1/3287 , G06F1/3228 , H04B17/318
Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.
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公开(公告)号：US20220358895A1
公开(公告)日：2022-11-10
申请号：US17752651
申请日：2022-05-24
Applicant: Apple Inc.
Inventor： Mahesh B. Chappalli , Christopher P. Tann , Peter F. Holland , Guy Côté , Stephan Lachowsky
Abstract: An electronic display pipeline may process image data for display on an electronic display. The electronic display pipeline may include burn-in compensation statistics collection circuitry and burn-in compensation circuitry. The burn-in compensation statistics collection circuitry may collect image statistics based at least in part on the image data. The statistics may estimate a likely amount of non-uniform aging of the sub-pixels of the electronic display. The burn-in compensation circuitry may apply a gain to sub-pixels of the image data to account for non-uniform aging of corresponding sub-pixels of the electronic display. The applied gain may be based at least in part on the image statistics collected by the burn-in compensation statistics collection circuitry.
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公开(公告)号：US11164540B2
公开(公告)日：2021-11-02
申请号：US16711319
申请日：2019-12-11
Applicant: Apple Inc.
Inventor： Peter F. Holland , Mahesh B. Chappalli , Yifan Zhang , Tae-Wook Koh
IPC: G09G5/10
Abstract: An electronic device may include an electronic display and a display pipeline. The electronic display may include multiple pixels to display images based at least in part on pixel data. The display pipeline may receive image data and process the image data to determine the pixel data. The display pipeline may include burn-in compensation circuitry to apply gains to the image data based at least in part on burn-in statistics to generate the pixel data. The gain to be applied to the image data for a pixel of the electronic display is determined by the burn-in compensation circuitry, based at least in part on an emission duty cycle of the pixel, to compensate the image data for the pixel for burn-in related aging of the pixel.
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公开(公告)号：US10983583B2
公开(公告)日：2021-04-20
申请号：US16110953
申请日：2018-08-23
Applicant: Apple Inc.
Inventor： Peter F. Holland , Christopher P. Tann , Malcolm D. Gray , Hari Ganesh R. Thirunageswaram , Kristan Jon Monsen
IPC: G09G5/36 , G06F1/32 , G06T1/60 , G09G5/00 , G06F1/3234 , G06F1/3296 , G06T15/00 , G06T1/20
Abstract: The configuration buffer may be divided into partitions that may effectively function as multiple linked configuration buffers. The linked partitions may each be associated with a portion of the display pipeline (e.g., an image process block) and may each be responsible for loading configuration entries into the programmable register(s) of a portion of the display pipeline. In this manner, the partitions may load the associated programmable register(s) of the display pipeline substantially simultaneously, reducing the time used to configure the entire display pipeline. Since configuration of the display pipeline may occur during the blanking period, a reduction in display pipeline configuration time may reduce the blanking period and increase the time for driving pixels of the display, thereby improving perceived image quality (e.g., pixel yield of the display panel).
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公开(公告)号：US10942559B2
公开(公告)日：2021-03-09
申请号：US16123848
申请日：2018-09-06
Applicant: Apple Inc.
Inventor： Peter F. Holland , Brad W. Simeral , Lior Zimet
IPC: G06F1/3234 , G06F1/3293 , G06F1/329
Abstract: An electronic device may include a display panel to display images based on corresponding image data and an image source to pre-render a flip-book including a first image frame for display at a first target presentation time and a second image frame for display at a second target presentation time. The electronic device may also include a display pipeline coupled between the display panel and the image source having image data processing circuitry to process image data for display. The electronic device may also include a controller to instruct the display pipeline to process image data, to determine a power-on time based on a target presentation time, and to instruct the display pipeline to power-gate the image data processing circuitry upon completion of the processing of image data and until the power-on time is reached.
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