公开(公告)号：US20200064902A1

公开(公告)日：2020-02-27

申请号：US16110953

申请日：2018-08-23

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Christopher P. Tann ,  Malcolm D. Gray ,  Hari Ganesh R. Thirunageswaram ,  Kristan Jon Monsen

IPC: G06F1/32 ,  G06T1/60 ,  G09G5/36

Abstract: The configuration buffer may be divided into partitions that may effectively function as multiple linked configuration buffers. The linked partitions may each be associated with a portion of the display pipeline (e.g., an image process block) and may each be responsible for loading configuration entries into the programmable register(s) of a portion of the display pipeline. In this manner, the partitions may load the associated programmable register(s) of the display pipeline substantially simultaneously, reducing the time used to configure the entire display pipeline. Since configuration of the display pipeline may occur during the blanking period, a reduction in display pipeline configuration time may reduce the blanking period and increase the time for driving pixels of the display, thereby improving perceived image quality (e.g., pixel yield of the display panel).

公开(公告)号：US10983583B2

公开(公告)日：2021-04-20

申请号：US16110953

申请日：2018-08-23

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Christopher P. Tann ,  Malcolm D. Gray ,  Hari Ganesh R. Thirunageswaram ,  Kristan Jon Monsen

IPC: G09G5/36 ,  G06F1/32 ,  G06T1/60 ,  G09G5/00 ,  G06F1/3234 ,  G06F1/3296 ,  G06T15/00 ,  G06T1/20

Abstract: The configuration buffer may be divided into partitions that may effectively function as multiple linked configuration buffers. The linked partitions may each be associated with a portion of the display pipeline (e.g., an image process block) and may each be responsible for loading configuration entries into the programmable register(s) of a portion of the display pipeline. In this manner, the partitions may load the associated programmable register(s) of the display pipeline substantially simultaneously, reducing the time used to configure the entire display pipeline. Since configuration of the display pipeline may occur during the blanking period, a reduction in display pipeline configuration time may reduce the blanking period and increase the time for driving pixels of the display, thereby improving perceived image quality (e.g., pixel yield of the display panel).