公开(公告)号：US20210200467A1

公开(公告)日：2021-07-01

申请号：US16730070

申请日：2019-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F3/06

Abstract: A memory controller interfaces with a non-volatile storage class memory (SCM) module over a heterogenous memory channel, and includes a command queue for receiving memory access commands. A memory interface queue is coupled to the command queue for holding outgoing commands. A non-volatile command queue is coupled to the command queue for storing non-volatile read commands that are placed in the memory interface queue. An arbiter selects entries from the command queue, and places them in the memory interface queue for transmission over a heterogenous memory channel. A control circuit is coupled to the heterogenous memory channel for receiving a ready response from the non-volatile SCM module indicating that responsive data is available for a non-volatile read command, and in response to receiving the ready response, causing a send command to be placed in the memory interface queue for commanding the non-volatile SCM module to send the responsive data.

公开(公告)号：US20210049062A1

公开(公告)日：2021-02-18

申请号：US16705913

申请日：2019-12-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James R. Magro ,  Kevin Michael Lepak ,  Vilas Sridharan

IPC: G06F11/07 ,  G06F11/10 ,  H03M13/29

Abstract: A data processing system includes a memory channel, a memory coupled to the memory channel, and a data processor. The data processor is coupled to the memory channel and accesses the memory over the memory channel using a packet structure defining a plurality of commands and having corresponding address bits, data bits, and user bits. The data processor communicates with the memory over the memory channel using a first type of error code. In response to a write access request, the data processor calculates a different, second type of error code and appends each bit of the second type of error code as a corresponding one of the user bits. The memory stores the user bits in the memory in response to a write command, and transfers the user bits to the data processor in a read response packet in response to a read command.

公开(公告)号：US10684969B2

公开(公告)日：2020-06-16

申请号：US15211815

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Jackson Peng ,  Hideki Kanayama

IPC: G06F13/16 ,  G06F13/40

Abstract: In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.

公开(公告)号：US20180113648A1

公开(公告)日：2018-04-26

申请号：US15299994

申请日：2016-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Scott P. Murphy ,  James R. Magro ,  Paramjit K. Lubana

IPC: G06F3/06 ,  G06F11/07

CPC classification number: G06F11/073 ,  G06F11/0793 ,  G06F13/16

Abstract: A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor includes a memory controller coupled to the memory channel and is adapted to access at least one rank of double data rate memory. The memory controller includes a command queue for storing received memory access requests, and an arbiter for picking memory access requests from the command queue, and then providing the memory access requests to the memory channel. The memory access requests are selected based on predetermined criteria, and in response to a mode register access request to quiesce pending operations. Additionally, the memory controller includes a mode register access controller that in response to the mode register access request, generates at least one corresponding mode register set command to a memory bus. The memory controller then relinquishes control of the memory bus to the arbiter thereafter.

公开(公告)号：US12299297B2

公开(公告)日：2025-05-13

申请号：US18216109

申请日：2023-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Jean J. Chittilappilly ,  Tahsin Askar ,  James R. Magro

IPC: G06F3/06

Abstract: A memory accessing circuit includes a memory controller for scheduling accesses to a memory, and a physical interface circuit for driving signals to the memory according to scheduled accesses and having configuration data. The memory controller comprises a memory and is responsive to a low power mode entry signal to save the configuration data in the memory. The physical interface circuit removes operating power from circuitry in the physical interface circuit that stores the configuration data in response to the memory controller completing a save operation.

公开(公告)号：US20250139022A1

公开(公告)日：2025-05-01

申请号：US18891278

申请日：2024-09-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James R. Magro

IPC: G06F13/16 ,  G06F13/40

Abstract: A memory controller includes a command queue stage for storing decoded memory access requests, a first arbiter operable to select first decoded memory access requests for a first pseudo channel from the command queue stage, and a second arbiter operable to select second decoded memory access requests for a second pseudo channel from the command queue stage. Each of the first arbiter and the second arbiter is operable to select a first streak of a first type of accesses, and to change to selecting a second streak of a second type of accesses in response to the first arbiter and the second arbiter meeting a cross mode condition.

公开(公告)号：US12243576B2

公开(公告)日：2025-03-04

申请号：US18198709

申请日：2023-05-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G06F9/24 ,  G06F1/3203 ,  G06F9/4401 ,  G11C11/406

Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.

公开(公告)号：US20250037750A1

公开(公告)日：2025-01-30

申请号：US18783900

申请日：2024-07-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Indrani Paul ,  Benjamin Tsien ,  James R. Magro

IPC: G11C11/4074 ,  G11C5/14 ,  G11C11/406

Abstract: The disclosed systems and methods include a control circuit for entering a low power state of a memory by preserving a context of the memory's controller and power gating the memory's physical layer. The context can be saved to a non-volatile memory device or by keeping a retention supply voltage to a register of the memory controller. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11995008B2

公开(公告)日：2024-05-28

申请号：US17354806

申请日：2021-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava ,  James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F13/16 ,  G11C11/4063

CPC classification number: G06F13/1642 ,  G11C11/4063

Abstract: A memory controller includes a command queue having an input for receiving memory access commands for a memory channel, and a number of entries for holding a predetermined number of memory access commands, and an arbiter that selects memory commands from the command queue for dispatch to one of a persistent memory and a DRAM memory coupled to the memory channel. The arbiter includes a first-tier sub-arbiter circuit coupled to the command queue for selecting candidate commands from among DRAM commands and persistent memory commands, and a second-tier sub-arbiter circuit coupled to the first-tier sub-arbiter circuit for receiving the candidate commands and selecting at least one command from among the candidate commands.

公开(公告)号：US20240112747A1

公开(公告)日：2024-04-04

申请号：US17957808

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Tahsin Askar ,  Naveen Davanam ,  Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G11C29/10

CPC classification number: G11C29/10

Abstract: A memory controller includes a first arbiter for selecting memory commands for dispatch to a memory over a first channel, a second arbiter for selecting memory commands for dispatch to the memory over a second channel, and a test circuit. The test circuit generates a respective testing sequence of read commands and write commands for each of the first channel and second channel, and causes the testing sequences to be transmitted over the first and second channels at least partially overlapping in time without selection by the first or second arbiters.