公开(公告)号：US20190196996A1

公开(公告)日：2019-06-27

申请号：US15851087

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  Ravindra N. Bhargava ,  Guanhao Shen ,  James Raymond Magro ,  Kevin M. Brandl

IPC: G06F13/30 ,  G06F13/16 ,  G06F3/06

CPC classification number: G06F13/30 ,  G06F3/061 ,  G06F3/0659 ,  G06F13/1642 ,  G06F13/1668

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory read requests have been sent to a memory device in a read mode of a data bus, the memory controller determines a threshold number of memory write requests to send to the memory device in an upcoming write mode is a number of outstanding memory write requests. Alternatively, the memory controller determines the threshold number of memory write requests to send to the memory device in an upcoming write mode is a maximum value of the number of outstanding memory write requests and a programmable value of the write burst length stored in a control register. Therefore, the write burst length is determined dynamically. Similarly, the read burst length is determined dynamically when the write mode ends.

公开(公告)号：US20190196987A1

公开(公告)日：2019-06-27

申请号：US15851324

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra N. Bhargava ,  James Raymond Magro ,  Kedarnath Balakrishnan ,  Jing Wang

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1636 ,  G06F13/1642 ,  G06F13/4234 ,  G11C11/40603

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses in a computing system are disclosed. In various embodiments, a computing system includes computing resources and a memory controller coupled to a memory device. The memory controller determines a memory request targets a given rank of multiple ranks. The memory controller determines a predicted latency for the given rank as an amount of time the pending queue in the memory controller for storing outstanding memory requests does not store any memory requests targeting the given rank. The memory controller determines the total bank latency as an amount of time for refreshing a number of banks which have not yet been refreshed in the given rank with per-bank refresh operations. If there are no pending requests targeting the given rank, each of the predicted latency and the total bank latency is used to select between per-bank and all-bank refresh operations.

公开(公告)号：US20190196720A1

公开(公告)日：2019-06-27

申请号：US15851414

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra N. Bhargava ,  James Raymond Magro ,  Kedarnath Balakrishnan ,  Kevin M. Brandl

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0653 ,  G06F3/0658 ,  G06F3/0673

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes one or more computing resources and a memory controller coupled to a memory device. The memory controller determines a memory access request targets a given bank of multiple banks. An access history is updated for the given bank based on whether the memory access request hits on an open page within the given bank and a page hit rate for the given bank is determined. The memory controller sets an idle cycle limit based on the page hit rate. The idle cycle limit is a maximum amount of time the given bank will be held open before closing the given bank while the bank is idle. The idle cycle limit is based at least in part on a page hit rate for the bank.

公开(公告)号：US10198216B2

公开(公告)日：2019-02-05

申请号：US15168043

申请日：2016-05-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/04 ,  G11C11/406 ,  G11C11/4072

Abstract: In one form, a data processing system includes a memory channel having a plurality of ranks, and a data processor. The data processor is coupled to the memory channel and is adapted to access each of the plurality of ranks. In response to detecting a predetermined event, the data processor selects an active rank of the plurality of ranks and places other ranks besides the active rank in a low power state, wherein the other ranks include at least one rank with a pending request at a time of detection of the predetermined event. The data processor subsequently processes a memory access request to the active rank.

公开(公告)号：US20170344309A1

公开(公告)日：2017-11-30

申请号：US15168043

申请日：2016-05-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0625 ,  G06F3/0673 ,  G06F13/16 ,  G06F13/1684 ,  G11C7/04 ,  G11C11/40615 ,  G11C11/4072

Abstract: In one form, a data processing system includes a memory channel having a plurality of ranks, and a data processor. The data processor is coupled to the memory channel and is adapted to access each of the plurality of ranks. In response to detecting a predetermined event, the data processor selects an active rank of the plurality of ranks and places other ranks besides the active rank in a low power state, wherein the other ranks include at least one rank with a pending request at a time of detection of the predetermined event. The data processor subsequently processes a memory access request to the active rank.

公开(公告)号：US20250139022A1

公开(公告)日：2025-05-01

申请号：US18891278

申请日：2024-09-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James R. Magro

IPC: G06F13/16 ,  G06F13/40

Abstract: A memory controller includes a command queue stage for storing decoded memory access requests, a first arbiter operable to select first decoded memory access requests for a first pseudo channel from the command queue stage, and a second arbiter operable to select second decoded memory access requests for a second pseudo channel from the command queue stage. Each of the first arbiter and the second arbiter is operable to select a first streak of a first type of accesses, and to change to selecting a second streak of a second type of accesses in response to the first arbiter and the second arbiter meeting a cross mode condition.

公开(公告)号：US12243576B2

公开(公告)日：2025-03-04

申请号：US18198709

申请日：2023-05-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G06F9/24 ,  G06F1/3203 ,  G06F9/4401 ,  G11C11/406

Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.

公开(公告)号：US12204754B2

公开(公告)日：2025-01-21

申请号：US16959503

申请日：2018-09-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James Raymond Magro

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/22

Abstract: Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.

公开(公告)号：US20240211173A1

公开(公告)日：2024-06-27

申请号：US18086942

申请日：2022-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  Jing Wang ,  Guanhao Shen

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0673

Abstract: A memory controller includes an arbiter. The arbiter is configured to elevate a priority of memory access requests that generate row activate commands in response to receiving a same-bank refresh request, and to send a same-bank refresh command in response to receiving the same-bank refresh request.

公开(公告)号：US11995008B2

公开(公告)日：2024-05-28

申请号：US17354806

申请日：2021-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava ,  James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F13/16 ,  G11C11/4063

CPC classification number: G06F13/1642 ,  G11C11/4063

Abstract: A memory controller includes a command queue having an input for receiving memory access commands for a memory channel, and a number of entries for holding a predetermined number of memory access commands, and an arbiter that selects memory commands from the command queue for dispatch to one of a persistent memory and a DRAM memory coupled to the memory channel. The arbiter includes a first-tier sub-arbiter circuit coupled to the command queue for selecting candidate commands from among DRAM commands and persistent memory commands, and a second-tier sub-arbiter circuit coupled to the first-tier sub-arbiter circuit for receiving the candidate commands and selecting at least one command from among the candidate commands.