公开(公告)号：US20200379814A1

公开(公告)日：2020-12-03

申请号：US16425878

申请日：2019-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Abhinav Vishnu ,  Thaleia Dimitra Doudali ,  Jagadish B. Kotra

IPC: G06F9/50 ,  G06N3/04 ,  G06K9/62

Abstract: Techniques for scheduling resources on a managed computer system are provided herein. A generative adversarial network generates predicted resource utilization. An orchestrator trains the generative adversarial network and provides the predicted resource utilization from the generative adversarial network to a resource scheduler for usage when the quality of the predicted resource utilization is above a threshold. The quality is measured as the ability of a generator component of the generative adversarial network to “fool” a discriminator component of the generative adversarial network into misclassifying the predicted resource utilization as being real (i.e., being of the type that is actually measured from the computer system).

公开(公告)号：US09983655B2

公开(公告)日：2018-05-29

申请号：US14963352

申请日：2015-12-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Mitesh R. Meswani ,  David A. Roberts ,  Dmitri Yudanov ,  Arkaprava Basu ,  Sergey Blagodurov

IPC: G06F1/00 ,  G06F1/32 ,  G06F9/38

CPC classification number: G06F1/3243 ,  G06F9/3885

Abstract: A method and apparatus for performing inter-lane power management includes de-energizing one or more execution lanes upon a determination that the one or more execution lanes are to be predicated. Energy from the predicated execution lanes is redistributed to one or more active execution lanes.

公开(公告)号：US20180018242A1

公开(公告)日：2018-01-18

申请号：US15207943

申请日：2016-07-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Taniya Siddiqua ,  Vilas Sridharan

IPC: G06F11/14 ,  G06F3/06

CPC classification number: G06F11/1471 ,  G06F2201/805 ,  G06F2201/84

Abstract: Methods and apparatus presented herein provide distributed checkpointing in a multi-node system, such as a network of servers in a data center. When checkpointing of application state data is needed in a node, the methods and apparatus determine whether checkpoint memory space is available in the node for checkpointing the application state data. If not enough checkpoint memory space is available in the node, the methods and apparatus request and find additional checkpoint memory space from other nodes in the system. In this manner, the methods and apparatus can checkpoint the application state data into available checkpoint memory spaces distributed among a plurality of nodes. This allows for high bandwidth and low latency checkpointing operations in the multi-node system.

公开(公告)号：US20170345512A1

公开(公告)日：2017-11-30

申请号：US15267092

申请日：2016-09-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Amro Awad ,  Sergey Blagodurov

IPC: G11C16/34 ,  G11C16/10 ,  G06F3/06 ,  G11C16/26

CPC classification number: G11C16/3495 ,  G11C16/10 ,  G11C16/26

Abstract: A non-volatile memory device having at least one non-volatile flash memory formatted with physical addresses to read and write data that is organized into blocks of data, wherein the blocks of data are organized into pages of data, and wherein the pages of data are organized into cells of data. The non-volatile memory device includes a non-volatile memory controller to direct read and write requests to the non-volatile flash memory for the storage and retrieval of data. The non-volatile memory controller includes a flash translation layer to correlate read and write requests for data having a logical address between the reading and writing the data to physical address location of the non-volatile flash memory. The flash translation layer, when writing to a physical address location, chooses between a wear-leveling circuit and a wear-limiting circuit to select the physical address location.

公开(公告)号：US20170277639A1

公开(公告)日：2017-09-28

申请号：US15361335

申请日：2016-11-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Amro Awad ,  Sergey Blagodurov ,  Arkaprava Basu ,  Mark H. Oskin ,  Gabriel H. Loh ,  Andrew G. Kegel ,  David S. Christie ,  Kevin J. McGrath

IPC: G06F12/1036 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/65 ,  G06F2212/683

Abstract: The described embodiments include a computing device with two or more translation lookaside buffers (TLB). During operation, the computing device updates an entry in the TLB based on a virtual address to physical address translation and metadata from a page table entry that were acquired during a page table walk. The computing device then computes, based on a lease length expression, a lease length for the entry in the TLB. Next, the computing device sets, for the entry in the TLB, a lease value to the lease length, wherein the lease value represents a time until a lease for the entry in the TLB expires, wherein the entry in the TLB is invalid when the associated lease has expired. The computing device then uses the lease value to control operations that are allowed to be performed using information from the entry in the TLB.

公开(公告)号：US09594521B2

公开(公告)日：2017-03-14

申请号：US14629014

申请日：2015-02-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Andrew G. Kegel

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0647 ,  G06F3/0607 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/067 ,  G06F12/0215 ,  G06F2212/654

Abstract: In one form, scheduling data migration comprises determining whether the data is likely to be used by an input/output (I/O) device, the data being at a location remote to the I/O device; and scheduling the data for migration from the remote location to a location local to the I/O device in response to determining that the data is likely to be used by the I/O device.

Abstract translation: 在一种形式中，调度数据迁移包括确定数据是否可能被输入/输出（I / O）设备使用，该数据位于远离I / O设备的位置; 并且响应于确定数据可能被I / O设备使用而调度用于从远程位置迁移到I / O设备本地的位置的数据。

公开(公告)号：US20160380921A1

公开(公告)日：2016-12-29

申请号：US14748209

申请日：2015-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov

IPC: H04L12/911 ,  G06F3/06

CPC classification number: H04L47/822 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/067 ,  H04L45/12 ,  H04L47/781

Abstract: A method of managing memory in a network of nodes includes identifying memory resources for each of the plurality of nodes connected to the network, storing memory resource information describing the memory resources, and based on the stored memory resource information, allocating a portion of the memory resources for execution of instructions in a workload, where at least a first node of the plurality of nodes is configured to execute the workload using the allocated portion of the memory resources.

Abstract translation: 一种在节点网络中管理存储器的方法包括：识别连接到网络的多个节点中的每一个的存储器资源，存储描述存储器资源的存储器资源信息，并且基于所存储的存储器资源信息，分配存储器的一部分 用于执行工作负载中的指令的资源，其中所述多个节点中的至少第一节点被配置为使用所分配的所述存储器资源部分来执行所述工作负载。

公开(公告)号：US20160378655A1

公开(公告)日：2016-12-29

申请号：US14752408

申请日：2015-06-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Gabriel H. Loh ,  Mitesh R. Meswani

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0897 ,  G06F12/1027 ,  Y02D10/13

Abstract: Systems, apparatuses, and methods for sorting memory pages in a multi-level heterogeneous memory architecture. The system may classify pages into a first “hot” category or a second “cold” category. The system may attempt to place the “hot” pages into the memory level(s) closest to the systems' processor cores. The system may track parameters associated with each page, with the parameters including number of accesses, types of accesses, power consumed per access, temperature, wearability, and/or other parameters. Based on these parameters, the system may generate a score for each page. Then, the system may compare the score of each page to a threshold. If the score of a given page is greater than the threshold, the given page may be designated as “hot”. If the score of the given page is less than the threshold, the given page may be designated as “cold”.

Abstract translation: 用于在多级异构存储器架构中分类存储器页面的系统，装置和方法。 系统可以将页面分类为第一个“热”类别或第二个“冷”类别。 系统可能会尝试将“热”页放置在最接近系统处理器内核的存储器级中。 系统可以跟踪与每个页面相关联的参数，其中参数包括访问次数，访问类型，每次访问消耗的功率，温度，耐磨性和/或其他参数。 基于这些参数，系统可以为每个页面生成分数。 然后，系统可以将每个页面的分数与阈值进行比较。 如果给定页面的分数大于阈值，则给定页面可能被指定为“热”。 如果给定页面的分数小于阈值，则给定的页面可以被指定为“冷”。

公开(公告)号：US20160188456A1

公开(公告)日：2016-06-30

申请号：US14587325

申请日：2014-12-31

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Gabriel H. Loh ,  Mauricio Breternitz

IPC: G06F12/02 ,  G06F12/12 ,  G06F9/54 ,  G11C14/00 ,  G11C11/34 ,  G06F12/06 ,  G06F12/08

CPC classification number: G06F9/48 ,  G06F12/0238 ,  G06F12/0811 ,  G06F2212/205 ,  G06F2212/2228 ,  G11C11/005

Abstract: In one form, a computer system includes a central processing unit, a memory controller coupled to the central processing unit and capable of accessing non-volatile random access memory (NVRAM), and an NVRAM-aware operating system. The NVRAM-aware operating system causes the central processing unit to selectively execute selected ones of a plurality of application programs, and is responsive to a predetermined operation to cause the central processing unit to execute a memory persistence procedure using the memory controller to access the NVRAM.

Abstract translation: 在一种形式中，计算机系统包括中央处理单元，耦合到中央处理单元并且能够访问非易失性随机存取存储器（NVRAM）的存储器控​​制器以及支持NVRAM的操作系统。 所述NVRAM感知操作系统使得所述中央处理单元选择性地执行多个应用程序中的选定的应用程序，并且响应于预定操作，以使所述中央处理单元执行使用所述存储器控制器访问所述NVRAM的存储器持久性过程 。

公开(公告)号：US12271318B2

公开(公告)日：2025-04-08

申请号：US17135657

申请日：2020-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Brandon K. Potter ,  Marko Scrbak ,  Sergey Blagodurov ,  Kishore Punniyamurthy ,  Nathaniel Morris

IPC: G06F12/12 ,  G06F12/0817

Abstract: Method and apparatus monitor eviction conflicts among cache directory entries in a cache directory and produce cache directory victim entry information for a memory manager. In some examples, the memory manager reduces future cache directory conflicts by changing a page level physical address assignment for a page of memory based on the produced cache directory victim entry information. In some examples, a scalable data fabric includes hardware control logic that performs the monitoring of the eviction conflicts among cache directory entries in the cache directory and produces the cache directory victim entry information.