公开(公告)号：US20160358638A1

公开(公告)日：2016-12-08

申请号：US14729504

申请日：2015-06-03

Applicant: Altera Corporation

Inventor： Martin Langhammer ,  Dana How

IPC: G11C8/18

CPC classification number: G11C8/18 ,  G06F1/10 ,  H03K19/17724

Abstract: An integrated circuit that includes different types of embedded functional blocks such as programmable logic blocks, memory blocks, and digital signal processing (DSP) blocks is provided. At least a first portion of the functional blocks on the integrated circuit may operate at a normal data rate using a core clock signal while a second portion of the functional blocks on the integrated circuit may operate at a 2× data rate that is double the normal data rate. To support this type of architecture, the integrated circuit may include clock generation circuitry that is capable of providing double pumped clock signals having clock pulses at rising and falling edges of the core clock signal, data concentration circuitry at the input of the 2× functional blocks, and data spreading circuitry at the output of the 2× functional blocks.

Abstract translation: 提供了包括不同类型的嵌入式功能块（例如可编程逻辑块，存储块和数字信号处理（DSP））的集成电路。 集成电路上的功能块的至少第一部分可以使用核心时钟信号以正常数据速率工作，而集成电路上的功能块的第二部分可以以正常的两倍的2倍数据速率工作 数据速率。 为了支持这种类型的架构，集成电路可以包括时钟生成电路，其能够提供在核心时钟信号的上升沿和下降沿具有时钟脉冲的双抽时钟信号，在2×功能块的输入处的数据集中电路 ，以及在2×功能块的输出端的数据扩展电路。

公开(公告)号：US09473112B1

公开(公告)日：2016-10-18

申请号：US14137086

申请日：2013-12-20

Applicant: Altera Corporation

Inventor： Ramanand Venkata ,  Dana How ,  Christopher Lane

IPC: G06F1/04 ,  H03K3/01 ,  H03K5/159

Abstract: Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one or more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.

公开(公告)号：US20150381707A1

公开(公告)日：2015-12-31

申请号：US14316400

申请日：2014-06-26

Applicant: ALTERA CORPORATION

Inventor： Dana How

IPC: H04L29/08

CPC classification number: H04L67/10 ,  H04L45/06

Abstract: Systems and methods are provided herein for implementing a Network-on-Chip (NoC) in a System-on-Chip (SoC) device. In some embodiments, an NoC may include a first node that transmits data to a second node, where data may be transmitted via either a first plane or a second plane. The first plane may utilize first logic at each of an output port of the first node, an input port of the second node, and at intermediary ports when transmitting the data to the second node. The second plane may utilize first logic at the output port of the first node and at the input port of the second node when transmitting the data to the second node, and may utilize second logic that is different from the first logic at the intermediary ports when transmitting the data to the second node.

Abstract translation: 本文提供的系统和方法用于在片上系统（SoC）设备中实现片上网络（NoC）。 在一些实施例中，NoC可以包括向第二节点发送数据的第一节点，其中数据可以经由第一平面或第二平面发送。 第一平面可以在第一节点的输出端口，第二节点的输入端口以及当将数据发送到第二节点时在中间端口处的每一个处使用第一逻辑。 第二平面可以在将数据发送到第二节点时在第一节点的输出端口处和第二节点的输入端口处利用第一逻辑，并且可以利用与中间端口处的第一逻辑不同的第二逻辑， 将数据发送到第二节点。

公开(公告)号：US09172379B1

公开(公告)日：2015-10-27

申请号：US14497827

申请日：2014-09-26

Applicant: Altera Corporation

Inventor： Dana How

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/177 ,  G06F17/50

CPC classification number: H03K19/1737 ,  G06F17/505 ,  G06F17/5054 ,  H03K19/17748

Abstract: Systems and methods relating to an elastic buffer for dynamically adjusting depth of a data-path implemented on an integrated circuit device. The device includes a first flip-flop, a second flip-flop, a multiplexer, and a controller. The first and second flip-flops are arranged in a cascade configuration with the multiplexer interposed therebetween. In certain embodiments, the multiplexer is capable of selecting between input received upstream and the output of the first flip-flop. The controller utilizes control logic to drive the first and second flip-flops and the multiplexer. The first and second flip-flops, and the multiplexer may represent an elastic buffer subunit corresponding to a single bit within a larger elastic buffer, in which a plurality of elastic buffer subunits are cascaded to form the elastic buffer along with a single shared controller.

Abstract translation: 与用于动态调整在集成电路装置上实现的数据路径的深度的弹性缓冲器有关的系统和方法。 该装置包括第一触发器，第二触发器，多路复用器和控制器。 第一和第二触发器被布置成级联配置，多路复用器插在它们之间。 在某些实施例中，多路复用器能够在上游接收的输入和第一触发器的输出之间进行选择。 控制器利用控制逻辑来驱动第一和第二触发器和多路复用器。 第一和第二触发器和复用器可以表示对应于较大弹性缓冲器内的单个位的弹性缓冲器子单元，其中多个弹性缓冲器子单元级联以与单个共享控制器一起形成弹性缓冲器。