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公开(公告)号：US20240235609A9
公开(公告)日：2024-07-11
申请号：US18493799
申请日：2023-10-24
Applicant: Apple Inc.
Inventor： Yashar Rajavi , Sohrab Emami-Neyestanak , Abbas Komijani
Abstract: A transceiver having a shared filter for both transmit and receive modes is disclosed. A transceiver includes a transmitter having an output coupled to a signal node, wherein the transmitter is configured to transmit signals onto the signal node during transceiver operation in a transmit mode. The transceiver also includes a receiver having an input coupled to the signal node, and configured to receive signals from the signal node during operation in the receive mode. The transceiver further includes a first filter coupled to the signal node, wherein the filter is shared by the transmitter and the receiver. The filter is coupled between the transceiver and a first terminal of a transmission line.
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公开(公告)号：US11990913B2
公开(公告)日：2024-05-21
申请号：US18079424
申请日：2022-12-12
Applicant: Apple Inc.
Inventor： Chen Zhai , Abbas Komijani
CPC classification number: H03L7/0818 , H03L7/085
Abstract: To increase the operating frequency range of the DLL while decreasing varactor sizes, coarse tuning circuitry may be implemented in a delay-locked loop (DLL). The DLL may include a voltage-controlled delay line (VCDL) including multiple switched capacitors coupled in parallel to each other. An electrical ground may be coupled to the parallel switched capacitors at a first node and a buffer and variable capacitor may be coupled to the parallel switched capacitors at a second node. The coarse tuning circuitry may be electrically coupled to a phase detector and to the multiple switched capacitors of the VCDL, such that the coarse tuning circuitry may receive a signal (e.g., an indication of a phase) from the phase detector and may adjust switched capacitor loading based on the signal received from the phase detector. Such a DLL implementation may increase DLL tuning range and decrease phase noise, among other advantages.
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公开(公告)号：US20240106440A1
公开(公告)日：2024-03-28
申请号：US18079424
申请日：2022-12-12
Applicant: Apple Inc.
Inventor： Chen Zhai , Abbas Komijani
CPC classification number: H03L7/0818 , H03L7/085
Abstract: To increase the operating frequency range of the DLL while decreasing varactor sizes, coarse tuning circuitry may be implemented in a delay-locked loop (DLL). The DLL may include a voltage-controlled delay line (VCDL) including multiple switched capacitors coupled in parallel to each other. An electrical ground may be coupled to the parallel switched capacitors at a first node and a buffer and variable capacitor may be coupled to the parallel switched capacitors at a second node. The coarse tuning circuitry may be electrically coupled to a phase detector and to the multiple switched capacitors of the VCDL, such that the coarse tuning circuitry may receive a signal (e.g., an indication of a phase) from the phase detector and may adjust switched capacitor loading based on the signal received from the phase detector. Such a DLL implementation may increase DLL tuning range and decrease phase noise, among other advantages.
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公开(公告)号：US11909355B2
公开(公告)日：2024-02-20
申请号：US17942850
申请日：2022-09-12
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani
CPC classification number: H03B5/12 , H03L1/00 , H04B1/40 , H03B2200/009 , H03B2200/0092 , H03B2201/038
Abstract: To prevent an undesired operating mode of voltage-controlled oscillation (VCO) circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), a supply reset and ramp pulse may be provided to the VCO circuitry when switching to a new mode, such that supply voltage to the VCO circuitry is reset (e.g., set to 0 V or another reference voltage), and gradually increased or ramped up back to a steady-state voltage (e.g., used to maintain a mode) within a time duration. Additionally or alternatively, a switch control bootstrap pulse may be provided to the VCO circuitry that is bootstrapped to (e.g., applied instantaneously or concurrently with) switching the VCO circuitry to the new mode. After a time duration, the VCO circuitry may switch back to a steady-state voltage (e.g., used to maintain the new mode).
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公开(公告)号：US11894866B2
公开(公告)日：2024-02-06
申请号：US17690867
申请日：2022-03-09
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani , Xinhua Chen
IPC: H04B1/04
CPC classification number: H04B1/04 , H04B2001/0408
Abstract: Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and/or a ground bounce.
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Patent Agency Ranking
46.发明公开公开(公告)号：US20230403013A1
公开(公告)日：2023-12-14
申请号：US17835292
申请日：2022-06-08
Applicant: Apple Inc.
Inventor： Reetika K Agarwal , Abbas Komijani , Hongrui Wang
CPC classification number: H03L7/0891 , H03L7/091 , H03L7/1976 , H03L7/185 , H03L7/099
Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.
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47.发明公开公开(公告)号：US20230378808A1
公开(公告)日：2023-11-23
申请号：US17751482
申请日：2022-05-23
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani
CPC classification number: H02J50/005 , H01F27/2804 , H02J50/12 , H01F27/027 , H01F2027/2809
Abstract: An electronic device may include wireless circuitry having a transformer adjustable between first, second, and third modes. The transformer may have first, second, third, and fourth inductors. The third inductor may be magnetically coupled to the first and second inductors with equal coupling constants. The fourth inductor may be magnetically coupled to the first and second inductors with inverse coupling constants. First and second adjustable capacitors coupled to the third and fourth inductors may receive control signals that place the transformer into a selected one of the first, second, or third modes. In the first mode the transformer exhibits a passband that overlaps first and second bands. In the second mode, the transformer passes signals in the second band while filtering interference in the first band. In the third mode, the transformer passes signals in the first band while filtering interference in the second band.
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公开(公告)号：US20230091785A1
公开(公告)日：2023-03-23
申请号：US17483005
申请日：2021-09-23
Applicant: Apple Inc.
Inventor： Reetika Kumari Agarwal , Abbas Komijani
Abstract: Embodiments disclosed herein relate to a low-voltage dropout regulator and more specifically to improving a power supply rejection ratio (PSRR) of the low dropout voltage regulator. The low dropout voltage regulator may be used to generate various voltages for integrated circuits of an electronic device. In some cases, a P-type metal-oxide-semiconductor (PMOS) low dropout (LDO) voltage regulator may be used. However, the PMOS LDO may not provide a sufficient PSRR or reduction in supply noise. To address these issues, an N-type metal-oxide-semiconductor (NMOS) LDO voltage regulator having an NMOS pass transistor may be used. The NMOS LDO may provide a lower impedance than the PMOS LDO. Further, the NMOS LDO may provide an increased bandwidth and consume a smaller physical area than the PMOS LDO.
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公开(公告)号：US20230090770A1
公开(公告)日：2023-03-23
申请号：US17748904
申请日：2022-05-19
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani
Abstract: To prevent an undesired operating mode of voltage-controlled oscillation (VCO) circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), a supply reset and ramp pulse may be provided to the VCO circuitry when switching to a new mode, such that supply voltage to the VCO circuitry is reset (e.g., set to 0 V or another reference voltage), and gradually increased or ramped up back to a steady-state voltage (e.g., used to maintain a mode) within a time duration. Additionally or alternatively, a switch control bootstrap pulse may be provided to the VCO circuitry that is bootstrapped to (e.g., applied instantaneously or concurrently with) switching the VCO circuitry to the new mode. After a time duration, the VCO circuitry may switch back to a steady-state voltage (e.g., used to maintain the new mode).
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公开(公告)号：US11573253B2
公开(公告)日：2023-02-07
申请号：US16923991
申请日：2020-07-08
Applicant: Apple Inc.
Inventor： Yashar Rajavi , Sohrab Emami-Neyestanak , Abbas Komijani
Abstract: A power detector circuit that rejects the common mode portion of a differential signal is disclosed. The circuit includes a differential input having first and second input nodes. Differential and common mode circuit paths are coupled to the differential input. The common mode circuit path includes first and second capacitors coupled to respective first terminals of first and second input nodes of the differential input. The second terminal of each of the first and second capacitors is coupled to a gate terminal of a first bias transistor. The common mode circuit path is configured to reject a common mode portion of a differential input signal provided to the differential input such that a differential output signal is indicative of an amount of power of a differential portion of the differential input signal.
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