公开(公告)号：US11990913B2

公开(公告)日：2024-05-21

申请号：US18079424

申请日：2022-12-12

Applicant: Apple Inc.

Inventor： Chen Zhai ,  Abbas Komijani

IPC: H03L7/081 ,  H03L7/085

CPC classification number: H03L7/0818 ,  H03L7/085

Abstract: To increase the operating frequency range of the DLL while decreasing varactor sizes, coarse tuning circuitry may be implemented in a delay-locked loop (DLL). The DLL may include a voltage-controlled delay line (VCDL) including multiple switched capacitors coupled in parallel to each other. An electrical ground may be coupled to the parallel switched capacitors at a first node and a buffer and variable capacitor may be coupled to the parallel switched capacitors at a second node. The coarse tuning circuitry may be electrically coupled to a phase detector and to the multiple switched capacitors of the VCDL, such that the coarse tuning circuitry may receive a signal (e.g., an indication of a phase) from the phase detector and may adjust switched capacitor loading based on the signal received from the phase detector. Such a DLL implementation may increase DLL tuning range and decrease phase noise, among other advantages.

公开(公告)号：US20240106440A1

公开(公告)日：2024-03-28

申请号：US18079424

申请日：2022-12-12

Applicant: Apple Inc.

Inventor： Chen Zhai ,  Abbas Komijani

IPC: H03L7/081 ,  H03L7/085

CPC classification number: H03L7/0818 ,  H03L7/085

Abstract: To increase the operating frequency range of the DLL while decreasing varactor sizes, coarse tuning circuitry may be implemented in a delay-locked loop (DLL). The DLL may include a voltage-controlled delay line (VCDL) including multiple switched capacitors coupled in parallel to each other. An electrical ground may be coupled to the parallel switched capacitors at a first node and a buffer and variable capacitor may be coupled to the parallel switched capacitors at a second node. The coarse tuning circuitry may be electrically coupled to a phase detector and to the multiple switched capacitors of the VCDL, such that the coarse tuning circuitry may receive a signal (e.g., an indication of a phase) from the phase detector and may adjust switched capacitor loading based on the signal received from the phase detector. Such a DLL implementation may increase DLL tuning range and decrease phase noise, among other advantages.