公开(公告)号：US08765556B2

公开(公告)日：2014-07-01

申请号：US12645834

申请日：2009-12-23

Applicant: Yu-Rung Hsu ,  Chen-Hua Yu ,  Chao-Cheng Chen ,  Ming-Huan Tsai ,  Hsien-Hsin Lin ,  Hsueh-Chang Sung

Inventor： Yu-Rung Hsu ,  Chen-Hua Yu ,  Chao-Cheng Chen ,  Ming-Huan Tsai ,  Hsien-Hsin Lin ,  Hsueh-Chang Sung

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a portion of the substrate, and strained structures disposed at either side of the portion of the substrate and formed of a semiconductor material different from the semiconductor substrate. The portion of the substrate is T shaped having a horizontal region and a vertical region that extends from the horizontal region in a direction away from a surface of the substrate.

Abstract translation: 本公开提供了一种半导体器件，其包括半导体衬底，设置在衬底的一部分上的栅极结构以及设置在衬底的该部分的任一侧的应变结构，并且由与半导体衬底不同的半导体材料形成。 衬底的部分是具有水平区域的垂直区域和从远离衬底表面的方向从水平区域延伸的垂直区域。

公开(公告)号：US20130273711A1

公开(公告)日：2013-10-17

申请号：US13449118

申请日：2012-04-17

Applicant: Chia-Chu Liu ,  Kuei-Shun Chen ,  Chih-Hsiung Peng ,  Chi-Kang Chang ,  Chiang Mu-Chi ,  Sheng-Yu Chang ,  Hua Feng Chen ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen

Inventor： Chia-Chu Liu ,  Kuei-Shun Chen ,  Chih-Hsiung Peng ,  Chi-Kang Chang ,  Chiang Mu-Chi ,  Sheng-Yu Chang ,  Hua Feng Chen ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen

IPC: H01L21/762

CPC classification number: H01L21/3086 ,  H01L21/76224

Abstract: A method for fabricating a device is disclosed. An exemplary method includes providing a substrate and forming a plurality of fins over the substrate. The method further includes forming a first opening in the substrate in a first longitudinal direction. The method further includes forming a second opening in the substrate in a second longitudinal direction. The first and second longitudinal directions are different. The method further includes depositing a filling material in the first and second openings.

Abstract translation: 公开了一种制造装置的方法。 一种示例性的方法包括提供衬底并在衬底上形成多个鳍。 该方法还包括在第一纵向方向上在基板中形成第一开口。 该方法还包括在第二纵向方向上在基板中形成第二开口。 第一和第二纵向是不同的。 该方法还包括在第一和第二开口中沉积填充材料。

公开(公告)号：US08529783B2

公开(公告)日：2013-09-10

申请号：US12798201

申请日：2010-03-30

Applicant: Huang-Ming Chen ,  Chun-Li Chou ,  Chao-Cheng Chen ,  Hun-Jan Tao

Inventor： Huang-Ming Chen ,  Chun-Li Chou ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC: H01L21/302

CPC classification number: H01L21/68735 ,  H01J37/3244 ,  H01J37/32642 ,  H01L21/02046 ,  H01L21/31116 ,  H01L21/67069 ,  Y10S156/914 ,  Y10S156/915 ,  Y10T279/23

Abstract: A method for preventing the formation of contaminating polymeric films on the backsides of semiconductor substrates includes providing an oxygen-impregnated focus ring and/or an oxygen-impregnated chuck that releases oxygen during etching operations. The method further provides delivering oxygen gas to the substrate by mixing oxygen in the cooling gas mixture, maintaining the focus ring at a temperature no greater than the substrate temperature during etching and cleaning the substrate using a two step plasma cleaning sequence that includes suspending the substrate above the chuck.

Abstract translation: 防止在半导体衬底的背面形成污染性聚合物膜的方法包括提供在蚀刻操作期间释放氧气的氧浸渍聚焦环和/或氧浸渍卡盘。 该方法还通过在冷却气体混合物中混合氧将氧气输送到衬底，在蚀刻和清洁衬底期间将聚焦环保持在不高于衬底温度的温度，使用包括悬浮衬底的两步骤等离子体清洗序列 在卡盘上方

公开(公告)号：US20130047101A1

公开(公告)日：2013-02-21

申请号：US13586856

申请日：2012-08-15

Applicant: Lih-Shyang Chen ,  Chih-Ching Yang ,  Chao-Cheng Chen ,  Chao-Yu Chen

Inventor： Lih-Shyang Chen ,  Chih-Ching Yang ,  Chao-Cheng Chen ,  Chao-Yu Chen

IPC: G06F3/01

CPC classification number: G06F3/0482 ,  G06F8/38

Abstract: A personal service menu construction system is provided for an application software to construct a homemade function menu, including: a selection module for setting required function options from a plurality of function options of the application software; an integration module for receiving the function options set by the selection module such that the function options set by the selection module are edited or packaged and integrated as a personal service menu; and a construction module for inputting the personal service menu to the application software. A personal service menu provision method is provided such that the personal service menu can be saved in a storage device and inputted to the same application software of another electronic device.

Abstract translation: 提供个人服务菜单构建系统，用于应用软件构建自制功能菜单，包括：选择模块，用于根据应用软件的多个功能选项设置所需的功能选项; 集成模块，用于接收由选择模块设置的功能选项，使得由选择模块设置的功能选项被编辑或打包并集成为个人服务菜单; 以及用于将个人服务菜单输入到应用软件的构建模块。 提供个人服务菜单提供方法，使得个人服务菜单可以保存在存储设备中并输入到另一电子设备的相同应用软件。

公开(公告)号：US20120108046A1

公开(公告)日：2012-05-03

申请号：US13281862

申请日：2011-10-26

Applicant: Yu Chao Lin ,  Ming-Ching Chang ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

Inventor： Yu Chao Lin ,  Ming-Ching Chang ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

IPC: H01L21/28 ,  H01L21/308

CPC classification number: H01L21/32139 ,  H01L21/0276 ,  H01L21/28194 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/823437 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成可图案化层。 该方法包括在可图案层上形成第一层。 该方法包括在第一层上形成第二层。 第二层比第一层薄得多。 该方法包括通过第一蚀刻工艺用光致抗蚀剂材料图案化第二层以形成图案化的第二层。 该方法包括通过第二蚀刻工艺将具有图案化的第二层的第一层图案化以形成图案化的第一层。 第一和第二层在第二蚀刻工艺期间具有显着不同的蚀刻速率。 该方法包括通过第三蚀刻工艺对具有图案化的第一层的图案化层进行图案化。

公开(公告)号：US07759239B1

公开(公告)日：2010-07-20

申请号：US12435552

申请日：2009-05-05

Applicant: Yu Chao Lin ,  De-Fang Chen ,  Chia-Wei Chang ,  Yih-Ann Lin ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Weng Cheng

Inventor： Yu Chao Lin ,  De-Fang Chen ,  Chia-Wei Chang ,  Yih-Ann Lin ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Weng Cheng

IPC: H01L21/3205

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/31144

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate layer over a substrate, forming a hard mask layer over a gate layer, forming a first material layer over the hard mask layer, forming a patterned photoresist layer having an opening over the first material layer, etching the first material layer through a cycle including forming a second material layer over the semiconductor device and etching the first and second material layers, repeating the cycle until the hard mask layer is exposed by a reduced opening, the reduced opening formed in a last cycle, etching the hard mask layer beneath the second opening to expose the gate layer, and patterning the gate layer using the hard mask layer. An etching selectivity of the first and second material layers is smaller than an etching selectivity of the second material layer and the photoresist layer.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成栅极层，在栅极层上形成硬掩模层，在硬掩模层上形成第一材料层，形成在第一材料层上具有开口的图案化光刻胶层，蚀刻第一材料 层，其包括在半导体器件上形成第二材料层并蚀刻第一和第二材料层，重复该循环，直到硬掩模层通过减小的开口暴露，在最后一个循环中形成的减小的开口，蚀刻硬 掩模层以暴露栅极层，并且使用硬掩模层图案化栅极层。 第一和第二材料层的蚀刻选择性小于第二材料层和光致抗蚀剂层的蚀刻选择性。

公开(公告)号：US20100068861A1

公开(公告)日：2010-03-18

申请号：US12339483

申请日：2008-12-19

Applicant: Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Joseph Lin ,  Jr Jung Lin ,  Yu Chao Lin ,  Chao-Cheng Chen ,  Kuo-Tai Huang

Inventor： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Joseph Lin ,  Jr Jung Lin ,  Yu Chao Lin ,  Chao-Cheng Chen ,  Kuo-Tai Huang

IPC: H01L21/8234 ,  H01L21/28

CPC classification number: H01L29/7848 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636

Abstract: Provided is a method of semiconductor fabrication including process steps allowing for defining and/or modifying a gate structure height during the fabrication process. The gate structure height may be modified (e.g., decreased) at one or more stages during the fabrication by etching a portion of a polysilicon layer included in the gate structure. The method includes forming a coating layer on the substrate and overlying the gate structure. The coating layer is etched back to expose a portion of the gate structure. The gate structure (e.g., polysilicon) is etched back to decrease the height of the gate structure.

Abstract translation: 提供了一种半导体制造方法，包括允许在制造过程期间限定和/或修改栅极结构高度的工艺步骤。 栅极结构高度可以在制造期间的一个或多个阶段被修改（例如减小），通过蚀刻包括在栅极结构中的多晶硅层的一部分。 该方法包括在衬底上形成覆盖层并覆盖栅极结构。 将涂层回蚀刻以露出栅极结构的一部分。 蚀刻栅极结构（例如，多晶硅）以降低栅极结构的高度。

公开(公告)号：US07511349B2

公开(公告)日：2009-03-31

申请号：US11207450

申请日：2005-08-19

Applicant: Ming-Huan Tsai ,  Fang-Cheng Chen ,  Chao-Cheng Chen ,  Syun-Ming Jang

Inventor： Ming-Huan Tsai ,  Fang-Cheng Chen ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/00 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76897 ,  H01L21/76804 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, and opens to the underlying layer. The hole includes a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer. At least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section area of the dielectric layer portion of the hole. The conformal barrier layer covers surfaces of the dielectric layer and the buffer layer in the hole. The hole is a via hole or a contact hole that is later filled with a conductive material to form a conductive via or a conductive contact.

Abstract translation: 集成电路芯片包括缓冲层，下层，电介质层，空穴和阻挡层。 缓冲层位于底层之上。 电介质层在缓冲层之上。 孔形成并延伸穿过介电层和缓冲层，并向下层开放。 该孔包括在缓冲层处的缓冲层部分和介电层处的电介质层部分。 孔的缓冲层部分的至少一部分具有比孔的电介质层部分的最小横截面面积更大的横截面面积。 保形阻挡层覆盖孔中的介电层和缓冲层的表面。 孔是通孔或接触孔，其后面填充有导电材料以形成导电通孔或导电接触。

公开(公告)号：US07186662B2

公开(公告)日：2007-03-06

申请号：US10964841

申请日：2004-10-13

Applicant: Chien-Hao Chen ,  Chia-Jen Chen ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Shih-Chang Chen

Inventor： Chien-Hao Chen ,  Chia-Jen Chen ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Shih-Chang Chen

IPC: H01L21/461

CPC classification number: H01L21/28123 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/31608 ,  H01L21/3185

Abstract: A method for forming a hard mask for gate electrode patterning in a semiconductor device is disclosed. The method includes providing a polysilicon layer to be etched and forming over the polysilicon layer, a nitride hardmask with a relatively high etch rate to hydrofluoric acid, as compared to the etch rate of silicon oxide. The polysilicon can then be patterned using the hardmask and the hardmask can be removed using hydrofluoric acid.

Abstract translation: 公开了一种在半导体器件中形成用于栅电极图案化的硬掩模的方法。 该方法包括提供待蚀刻并在多晶硅层上形成的多晶硅层，与氧化硅的蚀刻速率相比，具有对氢氟酸的蚀刻速率相对较高的氮化物硬掩模。 然后可以使用硬掩模对多晶硅进行图案化，并且可以使用氢氟酸去除硬掩模。

公开(公告)号：US07033518B2

公开(公告)日：2006-04-25

申请号：US10602968

申请日：2003-06-24

Applicant: Hui Ou Yang ,  Miao-Ju Hsu ,  Chao-Cheng Chen ,  Hun-Jan Tao

Inventor： Hui Ou Yang ,  Miao-Ju Hsu ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC: H01L21/00

CPC classification number: H01L21/31116 ,  H01J37/32935 ,  H01L22/26

Abstract: A method of etching multi-layer films, the method including: (1) etching a plurality of layers according to etching parameters, (2) determining a plurality of optical characteristics each associated with one of the plurality of layers and determined during the etching of the associated one of the plurality of layers, and (3) determining dynamic etch progressions each based on one of the plurality of optical characteristics that is associated with a particular one of the plurality of layers undergoing the etching.

Abstract translation: 一种蚀刻多层膜的方法，所述方法包括：（1）根据蚀刻参数蚀刻多个层，（2）确定多个光学特性，每个光学特性与所述多个层之一相关联并且在蚀刻期间确定 所述多个层中的相关联的一个层，以及（3）基于所述多个光学特性之一确定动态蚀刻进展，所述多个光学特性与经历所述蚀刻的所述多个层中的特定一个层相关联。