公开(公告)号：US07439613B2

公开(公告)日：2008-10-21

申请号：US10841656

申请日：2004-05-06

Applicant: Rajeev Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

Inventor： Rajeev Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

IPC: H01L21/44

CPC classification number: H01L23/49861 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45147

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes.

Abstract translation: 公开了一种半导体管芯封装。 在一个实施例中，半导体管芯封装具有衬底。 它包括（i）引线框架结构，其包括具有管芯附接表面的管芯附着区域和具有引线表面的引线，以及（ii）模制材料。 裸片附着表面和引线表面通过模制材料暴露。 半导体管芯在管芯附着区域上，并且半导体管芯电耦合到引线。 管芯附着表面和引线表面可以在不同的平面上。

公开(公告)号：US07393718B2

公开(公告)日：2008-07-01

申请号：US11202510

申请日：2005-08-11

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/44

CPC classification number: H01L23/145 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L25/074 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/181 ,  H05K3/3436 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the serves as the drain connections while the solder balls serve as the source and gate connections.

Abstract translation: 不包括成型体或封装的半导体器件。 半导体器件包括衬底和耦合到衬底的管芯。 芯片耦合到衬底，使得假设MOSFET型器件的管芯的源极和栅极区域耦合到衬底。 焊球靠近模具设置，使得当半导体器件耦合到印刷电路板时，暴露的表面用作漏极连接，而焊球用作源极和栅极连接。

公开(公告)号：US06992384B2

公开(公告)日：2006-01-31

申请号：US10741217

申请日：2003-12-19

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L23/34

CPC classification number: B23K1/0008 ,  B23K3/0623 ,  B23K2101/40 ,  H01L23/492 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

公开(公告)号：US20050280161A1

公开(公告)日：2005-12-22

申请号：US11202510

申请日：2005-08-11

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/14 ,  H01L23/373 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K3/34

CPC classification number: H01L23/145 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L25/074 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/181 ,  H05K3/3436 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the serves as the drain connections while the solder balls serve as the source and gate connections.

Abstract translation: 不包括成型体或封装的半导体器件。 半导体器件包括衬底和耦合到衬底的管芯。 芯片耦合到衬底，使得假设MOSFET型器件的管芯的源极和栅极区域耦合到衬底。 焊球靠近模具设置，使得当半导体器件耦合到印刷电路板时，暴露的表面用作漏极连接，而焊球用作源极和栅极连接。

公开(公告)号：US20050104168A1

公开(公告)日：2005-05-19

申请号：US10987550

申请日：2004-11-12

Applicant: Yoon-hwa Choi ,  Shi-baek Nam ,  O-seob Jeon ,  Rajeev Joshi ,  Maria Estacio

Inventor： Yoon-hwa Choi ,  Shi-baek Nam ,  O-seob Jeon ,  Rajeev Joshi ,  Maria Estacio

IPC: H01L23/31 ,  H01L23/433 ,  H01L23/495

CPC classification number: H01L23/4334 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/49568 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a molded leadless package, and a sawing type molded leadless package and method of manufacturing same. The molded leadless package includes a lead frame pad having first and second surfaces opposite to each other. A semiconductor chip is adhered to the first surface of the lead frame pad. A lead is electrically coupled to the semiconductor chip. A molding material covers the lead frame pad, the semiconductor chip, and the lead and exposes a portion of the lead and a portion of the second surface of the lead frame pad. A step difference is formed between a surface of the molding material covering the second surface of the lead frame pad and the second surface of the lead frame pad itself. The sawing type molded leadless package includes a short-circuit preventing member that is post-shaped or convex, and protruding from the lower surface of the die pad.

Abstract translation: 提供了一种模制无引线封装和锯切型模制无引线封装及其制造方法。 模制的无引线封装包括具有彼此相对的第一和第二表面的引线框架焊盘。 半导体芯片粘附到引线框架焊盘的第一表面。 引线电耦合到半导体芯片。 模制材料覆盖引线框架焊盘，半导体芯片和引线，并且暴露引线的一部分和引线框架焊盘的第二表面的一部分。 在覆盖引线框架焊盘的第二表面的成型材料的表面与引线框架焊盘本身的第二表面之间形成台阶差。 锯切型成型无引线封装包括后形状或凸形并从管芯焊盘的下表面突出的防短路部件。

公开(公告)号：US06633030B2

公开(公告)日：2003-10-14

申请号：US09944717

申请日：2001-08-31

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L3100

CPC classification number: H01L31/173 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00

Abstract: An optocoupler package is disclosed. The optocoupler package comprises a carrier substrate and a plurality of conductive regions on the carrier substrate. An optoelectronic device, an optically transmissive medium, and a plurality of conductive structures can be on the carrier substrate.

Abstract translation: 公开了一种光耦合器封装。 光耦合器封装包括载体衬底和载体衬底上的多个导电区域。 光电子器件，透光介质和多个导电结构可以在载体衬底上

公开(公告)号：US06566749B1

公开(公告)日：2003-05-20

申请号：US10050428

申请日：2002-01-15

Applicant: Rajeev Joshi ,  Steven Sapp

Inventor： Rajeev Joshi ,  Steven Sapp

IPC: H01L2310

CPC classification number: H01L24/85 ,  H01L23/04 ,  H01L23/3675 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor die package is disclosed. In one embodiment, the package includes a semiconductor die comprising a vertical power transistor. A source electrode and a gate contact region are at the first surface of the semiconductor die. A drain electrode is at the second surface of the semiconductor die. A base member is proximate to the second surface of the semiconductor die and is distal to the first surface of the semiconductor die and a cover disposed over the first surface of the semiconductor die. The cover is coupled to the base member and is adapted to transfer beat away from the semiconductor die.

Abstract translation: 公开了一种半导体管芯封装。 在一个实施例中，封装包括包括垂直功率晶体管的半导体管芯。 源极电极和栅极接触区域位于半导体管芯的第一表面。 漏极位于半导体管芯的第二表面。 基底构件靠近半导体管芯的第二表面，并且远离半导体管芯的第一表面，并且覆盖设置在半导体管芯的第一表面上。 盖子耦合到基座构件并且适于将跳动从半导体管芯移出。

公开(公告)号：US06489678B1

公开(公告)日：2002-12-03

申请号：US09285191

申请日：1999-03-15

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L2334

CPC classification number: B23K1/0008 ,  B23K3/0623 ,  B23K2101/40 ,  H01L23/492 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

Abstract translation: 一种用于改进的多芯片半导体封装的结构和方法，其将封装电阻降低到可忽略的水平，并提供优异的热性能。 通过提供电绝缘的引线框架来促进多个管芯的外壳，该引线框架通过层压材料的非导电层与共同的基底载体分开。 在每个引线框架中形成的腔内部附着有硅管芯。 然后通过分布在每个管芯的表面以及与每个管芯相邻的引线框架的边缘的焊料凸块的阵列来形成硅片的有源表面与印刷电路板的直接连接。

公开(公告)号：US6133634A

公开(公告)日：2000-10-17

申请号：US129663

申请日：1998-08-05

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: B23K1/00 ,  B23K3/06 ,  H01L23/492 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: B23K1/0008 ,  B23K3/0623 ,  H01L23/492 ,  B23K2201/40 ,  H01L2924/0002

Abstract: An improved semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. A silicon die is attached to a carrier (or substrate) that has a cavity substantially surrounding the die. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of the die as well as the edges of the carrier surrounding the die.

Abstract translation: 改进的半导体封装，将封装电阻降低到可忽略的水平，并提供出色的散热性能。 将硅片连接到具有基本上围绕裸片的空腔的载体（或基底）上。 然后通过分布在模具表面以及围绕模具的载体的边缘的焊料凸块的阵列制造硅片的有源表面与印刷电路板的直接连接。

公开(公告)号：US20120326287A1

公开(公告)日：2012-12-27

申请号：US13170017

申请日：2011-06-27

Applicant: Rajeev Joshi ,  Jaime A. Bayan ,  Ashok S. Prabhu

Inventor： Rajeev Joshi ,  Jaime A. Bayan ,  Ashok S. Prabhu

IPC: H01L23/495 ,  H05K1/11 ,  H01L21/82

CPC classification number: H01L23/49575 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0688 ,  H01L27/088 ,  H01L2224/05554 ,  H01L2224/40091 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/1306 ,  H01L2924/181 ,  H05K1/0296 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

Abstract: Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

Abstract translation: 描述了用于实现小尺寸功率转换器和小尺寸功率转换器装置的有效制造的方法和系统。