公开(公告)号：US20130118784A1

公开(公告)日：2013-05-16

申请号：US13293698

申请日：2011-11-10

Applicant: Cyprian Uzoh ,  Charles G. Woychik ,  Terrence Caskey ,  Belgacem Haba ,  Philip Damberg

Inventor： Cyprian Uzoh ,  Charles G. Woychik ,  Terrence Caskey ,  Belgacem Haba ,  Philip Damberg

IPC: H05K1/09 ,  H05K3/10

CPC classification number: H05K1/115 ,  H01L23/14 ,  H01L23/49827 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/03 ,  H05K1/09 ,  H05K3/42 ,  H05K2201/0141 ,  H05K2201/0175 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2203/025 ,  H05K2203/1105 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter.

公开(公告)号：US20120326326A1

公开(公告)日：2012-12-27

申请号：US13168839

申请日：2011-06-24

Applicant: Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed

Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/3212 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/7688 ,  H01L23/481 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有共面或平坦的顶表面。 另一个特征是形成互连结构的方法，其导致互连结构具有相对于衬底顶表面向上倾斜大于零的表面。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

公开(公告)号：US07329335B2

公开(公告)日：2008-02-12

申请号：US10459323

申请日：2003-06-10

Applicant: Homayoun Talieh ,  Cyprian Uzoh ,  Bulent M. Basol

Inventor： Homayoun Talieh ,  Cyprian Uzoh ,  Bulent M. Basol

IPC: B23H3/00 ,  C25F3/30 ,  B23H7/12

CPC classification number: B23H3/04 ,  B23H5/08 ,  C25D5/08 ,  C25D17/00 ,  C25D17/001 ,  C25D17/005 ,  C25F7/00 ,  H01L21/2885

Abstract: Substantially uniform deposition of conductive material on a surface of a substrate, which substrate includes a semiconductor wafer, from an electrolyte containing the conductive material can be provided by way of a particular device which includes first and second conductive elements. The first conductive element can have multiple electrical contacts, of identical or different configurations, or may be in the form of a conductive pad, and can contact or otherwise electrically interconnect with the substrate surface over substantially all of the substrate surface. Upon application of a potential between the first and second conductive elements while the electrolyte makes physical contact with the substrate surface and the second conductive element, the conductive material is deposited on the substrate surface. It is possible to reverse the polarity of the voltage applied between the anode and the cathode so that electro-etching of deposited conductive material can be performed.

Abstract translation: 可以通过包括第一和第二导电元件的特定装置来提供导电材料在包含导电材料的电解质的衬底的包括半导体晶片的表面上的基本均匀沉积。 第一导电元件可以具有相同或不同构造的多个电触点，或者可以是导电焊盘的形式，并且可以在基本上所有的衬底表面上与衬底表面接触或以其他方式电互连。 当在电解质与衬底表面和第二导电元件物理接触的同时在第一和第二导电元件之间施加电势时，导电材料沉积在衬底表面上。 可以使施加在阳极和阴极之间的电压的极性反转，从而可以对沉积的导电材料进行电蚀刻。

公开(公告)号：US20070135022A1

公开(公告)日：2007-06-14

申请号：US11704631

申请日：2007-02-09

Applicant: Bulent Basol ,  Cyprian Uzoh

Inventor： Bulent Basol ,  Cyprian Uzoh

IPC: B24B49/00

CPC classification number: B24B57/02 ,  B24B37/042 ,  C23C18/1617 ,  C23C18/38 ,  C25D7/123 ,  C25D21/04 ,  C25D21/18 ,  H01L21/2885

Abstract: The present invention provides an apparatus for wet processing of a conductive layer using a degassed process solution such as a degassed electrochemical deposition solution, a degassed electrochemical polishing solution, a degassed deposition solution, and a degassed cleaning solution. The technique includes degassing the process solution before delivering the degassed process solution to a processing unit or degassing the process solution in situ, within the processing unit.

Abstract translation: 本发明提供一种使用脱气的电解沉积溶液，脱气电化学抛光溶液，脱气沉积溶液和脱气清洗溶液等脱气工艺溶液对导电层进行湿法加工的设备。 该技术包括在将脱气的处理溶液递送到处理单元之前对处理溶液进行脱气或在处理单元内原位脱气处理溶液。

公开(公告)号：US20060009033A1

公开(公告)日：2006-01-12

申请号：US11226511

申请日：2005-09-13

Applicant: Bulent Basol ,  Cyprian Uzoh

Inventor： Bulent Basol ,  Cyprian Uzoh

IPC: H01L21/461 ,  C25D17/00

CPC classification number: C25D17/001 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76877

Abstract: The process of the present invention forms copper interconnects in a semiconductor wafer surface. During the process, initially, narrow and large features are provided in the top surface of the wafer, and then a primary copper layer is deposited by employing an electrochemical deposition process. The primary copper layer completely fills the features and forms a planar surface over the narrow feature and a non-planar surface over the large feature. By employing an electrochemical mechanical deposition process, a secondary copper layer is deposited onto the primary copper layer to form a planar copper layer over the narrow and large features. After this process step, the thickness of the planar copper layer is reduced using an electropolishing process.

Abstract translation: 本发明的方法在半导体晶片表面中形成铜互连。 在该过程中，最初，在晶片的顶表面中提供窄且大的特征，然后通过使用电化学沉积工艺沉积初级铜层。 初级铜层完全填满了特征，并在狭窄的特征上形成一个平坦的表面，在大的特征上形成一个非平面的表面。 通过采用电化学机械沉积工艺，将二次铜层沉积在初级铜层上，以形成窄和大特征上的平面铜层。 在该工艺步骤之后，使用电解抛光工艺来减小平面铜层的厚度。

公开(公告)号：US20060006060A1

公开(公告)日：2006-01-12

申请号：US11225913

申请日：2005-09-13

Applicant: Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

Inventor： Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

IPC: C25D17/00

CPC classification number: C25D5/02 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76877

Abstract: An apparatus for processing a material on a surface of a wafer having a diameter includes a cavity defined by a peripheral wall terminating at a peripheral edge and having at least one lateral dimension smaller than the wafer diameter and at least one lateral dimension larger than the wafer diameter and configured to hold a process solution proximate to the peripheral edge such that the process solution will always contact a first wafer surface region, a head configured to hold the wafer above the cavity peripheral edge so that the surface of the wafer faces the cavity, and an electrical contact member positioned outside the cavity peripheral wall and configured to contact a second wafer surface region where the lateral dimension of the cavity is smaller than the wafer diameter and to maintain electrical contact with the wafer when the wafer is moved relative to the contact member. Advantages of the invention include substantially full surface treatment of the wafer.

Abstract translation: 一种用于处理具有直径的晶片表面上的材料的设备包括由外围壁限定的空腔，该外围壁终止于外围边缘并具有至少一个小于晶片直径的横向尺寸和至少一个大于晶片的横向尺寸 并且被配置为将处理溶液保持靠近外围边缘，使得处理溶液将始终接触第一晶片表面区域，头部被配置为将晶片保持在空腔周边边缘上方，使得晶片的表面面向空腔， 以及电接触构件，其定位在所述腔周壁外部并且被配置为接触所述腔的横向尺寸小于所述晶片直径的第二晶片表面区域，并且当所述晶片相对于所述触点移动时与所述晶片保持电接触 会员。 本发明的优点包括晶片的基本全表面处理。

公开(公告)号：US06943112B2

公开(公告)日：2005-09-13

申请号：US10379265

申请日：2003-03-03

Applicant: Bulent M. Basol ,  Cyprian Uzoh

Inventor： Bulent M. Basol ,  Cyprian Uzoh

IPC: H01L21/288 ,  H01L21/321 ,  H01L21/768 ,  H01L21/44

CPC classification number: C25D17/001 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76877

Abstract: The process of the present invention forms copper interconnects in a semiconductor wafer surface. During the process, initially, narrow and large features are provided in the top surface of the wafer, and then a primary copper layer is deposited by employing an electrochemical deposition process. The primary copper layer completely fills the features and forms a planar surface over the narrow feature and a non-planar surface over the large feature. By employing an electrochemical mechanical deposition process, a secondary copper layer is deposited onto the primary copper layer to form a planar copper layer over the narrow and large features. After this process step, the thickness of the planar copper layer is reduced using an electropolishing process.

Abstract translation: 本发明的方法在半导体晶片表面中形成铜互连。 在该过程中，最初，在晶片的顶表面中提供窄且大的特征，然后通过使用电化学沉积工艺沉积初级铜层。 初级铜层完全填满了特征，并在狭窄的特征上形成一个平坦的表面，在大的特征上形成一个非平面的表面。 通过采用电化学机械沉积工艺，将二次铜层沉积在初级铜层上，以形成窄和大特征上的平面铜层。 在该工艺步骤之后，使用电解抛光工艺来减小平面铜层的厚度。

公开(公告)号：US20050145484A1

公开(公告)日：2005-07-07

申请号：US11057297

申请日：2005-02-10

Applicant: Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

Inventor： Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

IPC: B08B1/04 ,  B24B37/04 ,  B24B53/00 ,  B24B53/007 ,  C25D5/22 ,  C25D7/12 ,  C25F3/16 ,  H01L21/288 ,  H01L21/304 ,  H01L21/768 ,  B23H7/26

CPC classification number: B24B53/017 ,  B24B37/04 ,  B24B53/001 ,  C25D5/22 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76877

Abstract: Systems and methods to remove or lessen the size of metal particles that have formed on, and to limit the rate at which metal particles form or grow on, workpiece surface influencing devices used during electrodeposition are presented. According to an exemplary method, the workpiece surface influencing device is occasionally placed in contact with a conditioning substrate coated with an inert material, and the bias applied to the electrodeposition system is reversed. According to another exemplary method, the workpiece surface influencing device is conditioned using mechanical contact members, such as brushes, and conditioning of the workpiece surface influencing device occurs, for example, through physical brushing of the workpiece surface influencing device with the brushes. According to a further exemplary method, the workpiece surface influencing device is rotated in different direction during electrodeposition.

Abstract translation: 提出了用于去除或减小在电沉积期间使用的工件表面影响装置上形成金属颗粒的尺寸并限制金属颗粒形成或生长的速率的系统和方法。 根据示例性的方法，工件表面影响装置偶尔地与涂覆有惰性材料的调理基板接触，并且施加到电沉积系统的偏压被反转。 根据另一示例性方法，使用诸如刷子的机械接触构件对工件表面影响装置进行调节，并且例如通过用刷子物理刷刷工件表面影响装置来发生工件表面影响装置的调节。 根据另一示例性方法，在电沉积期间，工件表面影响装置在不同方向上旋转。

公开(公告)号：US20050042873A1

公开(公告)日：2005-02-24

申请号：US10925358

申请日：2004-08-23

Applicant: Cyprian Uzoh ,  Bulent Basol ,  Homayoun Talieh

Inventor： Cyprian Uzoh ,  Bulent Basol ,  Homayoun Talieh

IPC: C25F3/14 ,  H01L21/288 ,  H01L21/321 ,  H01L21/768 ,  H01L23/532 ,  H01L27/10 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76843 ,  C25F3/14 ,  H01L21/288 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods to operate upon a nonplanar top surface of a conductive surface layer of a workpiece, so as to, for example, preserve the structural integrity of a dielectric film layer disposed below the conductive surface layer, are presented. According to an exemplary method, a layer of conducting material such as a conducting paste is applied over the nonplanar top surface of the conductive surface layer to obtain a planar top surface. At least a portion of the conducting material layer and at least a portion of the conductive surface layer are removed in a planar manner to at least partially planarize the nonplanar top surface. The conducting material layer may be annealed so that the conducting material layer diffuses with the conductive surface layer prior to removal of at least the portions of conducting material layer and the conductive surface layer.

Abstract translation: 提供了在工件的导电表面层的非平面顶表面上操作以便例如保持设置在导电表面层下方的电介质膜层的结构完整性的系统和方法。 根据示例性方法，在导电表面层的非平面顶表面上施加诸如导电浆料的导电材料层以获得平坦的顶表面。 导电材料层的至少一部分和导电表面层的至少一部分以平面方式去除，以至少部分平坦化非平面顶表面。 导电材料层可以退火，使得在去除至少导电材料层和导电表面层的部分之前，导电材料层与导电表面层扩散。

公开(公告)号：US06852208B2

公开(公告)日：2005-02-08

申请号：US10265460

申请日：2002-10-03

Applicant: Jalal Ashjaee ,  Boguslaw Nagorski ,  Bulent M. Basol ,  Homayoun Talieh ,  Cyprian Uzoh

Inventor： Jalal Ashjaee ,  Boguslaw Nagorski ,  Bulent M. Basol ,  Homayoun Talieh ,  Cyprian Uzoh

IPC: C25D7/12 ,  C25F7/00 ,  C25D5/00

CPC classification number: C25F7/00 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885

Abstract: Deposition of conductive material on or removal of conductive material from a workpiece frontal side of a semiconductor workpiece is performed by providing an anode having an anode area which is to face the workpiece frontal side, and electrically connecting the workpiece frontal side with at least one electrical contact, outside of the anode area, by pushing the electrical contact and the workpiece frontal side into proximity with each other. A potential is applied between the anode and the electrical contact, and the workpiece is moved with respect to the anode and the electrical contact. Full-face electroplating or electropolishing over the workpiece frontal side surface, in its entirety, is thus permitted.

Abstract translation: 通过提供具有正面与工件正面的阳极区域并将工件正面与至少一个电气电连接的阳极进行导电材料沉积在导电材料上或从半导体工件的工件正面去除导电材料 通过将电触点和工件正面推入彼此靠近，在阳极区域外部接触。 在阳极和电接触之间施加电位，并且工件相对于阳极和电触点移动。 因此允许在工件正面侧面上进行全面电镀或电解抛光。