公开(公告)号：US10074564B2

公开(公告)日：2018-09-11

申请号：US15878486

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Ruilong Xie ,  Lars Liebmann

IPC: H01L29/417 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/66 ,  H01L23/522 ,  H01L29/40 ,  H01L29/78 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/28247 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66613 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Disclosed are methods and integrated circuit (IC) structures. The methods enable formation of a gate contact on a gate above (or close thereto) an active region of a field effect transistor (FET) and provide protection against shorts between the gate contact and metal plugs on source/drain regions and between the gate and source/drain contacts to the metal plugs. A gate with a dielectric cap and dielectric sidewall spacer is formed on a FET channel region. Metal plugs with additional dielectric caps are formed on the FET source/drain regions such that the dielectric sidewall spacer is between the gate and the metal plugs and between the dielectric cap and the additional dielectric caps. The dielectric cap, dielectric sidewall spacer and additional dielectric caps are different materials preselected to be selectively etchable, allowing for misalignment of a contact opening to the gate without risking exposure of any metal plugs and vice versa.

公开(公告)号：US20180166335A1

公开(公告)日：2018-06-14

申请号：US15878486

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Ruilong Xie ,  Lars Liebmann

IPC: H01L21/768 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238

CPC classification number: H01L21/76897 ,  H01L21/28247 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66613 ,  H01L29/785 ,  H01L2029/7858

Abstract: Disclosed are methods and integrated circuit (IC) structures. The methods enable formation of a gate contact on a gate above (or close thereto) an active region of a field effect transistor (FET) and provide protection against shorts between the gate contact and metal plugs on source/drain regions and between the gate and source/drain contacts to the metal plugs. A gate with a dielectric cap and dielectric sidewall spacer is formed on a FET channel region. Metal plugs with additional dielectric caps are formed on the FET source/drain regions such that the dielectric sidewall spacer is between the gate and the metal plugs and between the dielectric cap and the additional dielectric caps. The dielectric cap, dielectric sidewall spacer and additional dielectric caps are different materials preselected to be selectively etchable, allowing for misalignment of a contact opening to the gate without risking exposure of any metal plugs and vice versa.

公开(公告)号：US20180083121A1

公开(公告)日：2018-03-22

申请号：US15268751

申请日：2016-09-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Puneet Harischandra Suvarna ,  Steven J. Bentley ,  Daniel Chanemougame

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/306 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L29/0847 ,  H01L29/165

Abstract: One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure above a substrate, performing an epi deposition process to simultaneously form at least a portion of a bottom source/drain region and at least a portion of a top source/drain region during the epi deposition process and, after performing the epi deposition process, forming a gate structure around a portion of the vertically oriented channel semiconductor structure.

公开(公告)号：US09620505B2

公开(公告)日：2017-04-11

申请号：US15073100

申请日：2016-03-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC ,  GLOBALFOUNDRIES INC.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh ,  Kejia Wang ,  Daniel Chanemougame

IPC: H01L21/30 ,  H01L27/088 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795

Abstract: A semiconductor device which includes: a substrate; a first set of fins above the substrate of a first semiconductor material; a second set of fins above the substrate and of a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer. The isolation region may be an isolation pillar or an isolation trench.

公开(公告)号：US20150333086A1

公开(公告)日：2015-11-19

申请号：US14280998

申请日：2014-05-19

Applicant: STMICROELECTRONICS, INC ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Xiuyu CAI ,  Ruilong XIE ,  Chun-chen Yeh ,  Kejia Wang ,  Daniel Chanemougame

IPC: H01L27/12 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795

Abstract: A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions.

Abstract translation: 制造半导体器件的方法可以包括在衬底上方形成彼此横向相邻并且包括第一半导体材料的第一和第二半导体区域。 第一半导体区域可以具有比第二半导体区域更大的垂直厚度并且限定具有第二半导体区域的侧壁。 该方法还可以包括在第二半导体区域的上方形成并邻近侧壁的间隔物，以及在第二半导体区域上方并邻近间隔物形成第三半导体区域，其中第二半导体区域包括与第一半导体材料不同的第二半导体材料 。 该方法还可以包括在间隔物下面移除间隔物和第一半导体材料的部分，从第一半导体区域形成第一组散热片，以及从第二和第三半导体区域形成第二组散热片。

公开(公告)号：US10692991B2

公开(公告)日：2020-06-23

申请号：US16123160

申请日：2018-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Julien Frougier ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3065

Abstract: Disclosed are structures including a gate-all-around field effect transistor (GAAFET) with air-gap inner spacers. The GAAFET includes a stack of nanoshapes that extend laterally between source/drain regions, a gate that wraps around a center portion of each nanoshape, and a gate sidewall spacer on external sidewalls of the gate. The GAAFET also includes air-gap inner spacers between the gate and the source/drain regions. Each air-gap inner spacer includes: two vertical sections within the gate sidewall spacer on opposing sides of the stack and adjacent to a source/drain region; and horizontal sections below the nanoshapes and extending laterally between the vertical sections. Also discloses are methods of forming the structures and the method include forming preliminary inner spacers in inner spacer cavities prior to source/drain region formation. After source/drain regions are formed, the preliminary inner spacers are removed and the cavities are sealed off, thereby forming the air-gap inner spacers.

公开(公告)号：US20200075456A1

公开(公告)日：2020-03-05

申请号：US16114600

申请日：2018-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel Chanemougame ,  Julien Frougier ,  Ruilong Xie

IPC: H01L23/48 ,  H01L21/768 ,  H01L29/08 ,  H01L23/532

Abstract: Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A contact structure is formed that includes a first contact arranged over a source/drain region and a second contact arranged over the first contact. A dielectric cap is formed over the second contact. A via is formed that extends in a vertical direction through the dielectric cap to the second contact. An interconnect is formed over the dielectric cap, and is connected by the via with the second contact.

公开(公告)号：US20190386107A1

公开(公告)日：2019-12-19

申请号：US16555734

申请日：2019-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hao Tang ,  Cheng Chi ,  Daniel Chanemougame ,  Lars W. Liebmann ,  Mark V. Raymond

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535 ,  H01L29/78 ,  H01L29/45

Abstract: One illustrative transistor device disclosed herein includes, among other things, a gate positioned above a semiconductor substrate, the gate comprising a gate structure, a conductive source/drain metallization structure positioned adjacent the gate, the conductive source/drain metallization structure having a front face, and an insulating spacer that is positioned on and in contact with at least a portion of the front face of the conductive source/drain metallization structure. In this example, the device also includes a gate contact opening that exposes at least a portion of the insulating spacer and a portion of an upper surface of the gate structure and a conductive gate contact structure positioned in the gate contact opening, wherein the conductive gate contact structure contacts at least a portion of the insulating spacer and wherein the conductive gate contact structure is conductively coupled to the gate structure.

公开(公告)号：US10483363B2

公开(公告)日：2019-11-19

申请号：US15581105

申请日：2017-04-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hao Tang ,  Cheng Chi ,  Daniel Chanemougame ,  Lars W. Liebmann ,  Mark V. Raymond

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535 ,  H01L29/45 ,  H01L29/78

Abstract: One method includes forming a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap positioned above the gate structure, forming a conductive source/drain metallization structure adjacent the gate in each of the source/drain regions and forming a recess in each of the conductive source/drain metallization structures. The method further includes forming a spacer structure that comprises recess filling portions that substantially fill the recesses and a portion that extends across the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, forming an insulating material within the spacer structure and on the exposed portion of the gate cap, forming a gate contact opening that exposes a portion of an upper surface of the gate structure and forming a conductive gate contact structure (CB) in the conductive gate contact opening.

公开(公告)号：US10468300B2

公开(公告)日：2019-11-05

申请号：US15641927

申请日：2017-07-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andre Labonte ,  Lars Liebmann ,  Daniel Chanemougame ,  Chanro Park ,  Nigel Cave ,  Vimal Kamineni

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/311 ,  H01L27/088 ,  H01L29/08 ,  H01L23/535 ,  H01L29/06

Abstract: A method of manufacturing a semiconductor device is provided including forming raised source and drain regions on a semiconductor layer, forming a first insulating layer over the semiconductor layer, forming a first contact to one of the source and drain regions in the first insulating layer, forming a second insulating layer over the first contact, forming a trench in the second insulating layer to expose the first contact, removing a portion of the first contact below the trench, thereby forming a recessed surface of the first contact, removing a portion of the first insulating layer, thereby forming a recess in the trench and exposing a portion of a sidewall of the first contact below the recessed surface of the first contact, and filling the trench and the recess formed in the trench with a contact material to form a second contact in contact with the first contact.