中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

55 records (took 0.022 seconds)

    Multi-die dot-product engine to provision large scale machine learning inference applications
    42.
    发明授权
    Multi-die dot-product engine to provision large scale machine learning inference applications 有权

    公开(公告)号：US11947928B2

    公开(公告)日：2024-04-02

    申请号：US17017557

    申请日：2020-09-10

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Craig Warner ,  Eun Sub Lee ,  Sai Rahul Chalamalasetti ,  Martin Foltin

    IPC: G06F7/544 ,  G06F9/38 ,  G06F9/52 ,  G06F40/20 ,  G06N3/063

    CPC classification number: G06F7/5443 ,  G06F9/3867 ,  G06F9/522 ,  G06F40/20 ,  G06N3/063

    Abstract: Systems and methods are provided for a multi-die dot-product engine (DPE) to provision large-scale machine learning inference applications. The multi-die DPE leverages a multi-chip architecture. For example, a multi-chip interface can include a plurality of DPE chips, where each DPE chip performs inference computations for performing deep learning operations. A hardware interface between a memory of a host computer and the plurality of DPE chips communicatively connects the plurality of DPE chips to the memory of the host computer system during an inference operation such that the deep learning operations are spanned across the plurality of DPE chips. Due to the multi-die architecture, multiple silicon devices are allowed to be used for inference, thereby enabling power-efficient inference for large-scale machine learning applications and complex deep neural networks. The multi-die DPE can be used to build a multi-device DNN inference system performing specific applications, such as object recognition, with high accuracy.

    Vertical JFET device for memristor array interface
    44.
    发明授权
    Vertical JFET device for memristor array interface 有权

    公开(公告)号：US11322545B2

    公开(公告)日：2022-05-03

    申请号：US17041382

    申请日：2018-04-27

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Amit S. Sharma ,  John Paul Strachan ,  Martin Foltin

    IPC: H01L29/66 ,  H01L21/02 ,  H01L27/24 ,  H01L29/161 ,  H01L29/808

    Abstract: Devices and methods are provided. In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.

    MULTI-DIE DOT-PRODUCT ENGINE TO PROVISION LARGE SCALE MACHINE LEARNING INFERENCE APPLICATIONS
    45.
    发明申请
    MULTI-DIE DOT-PRODUCT ENGINE TO PROVISION LARGE SCALE MACHINE LEARNING INFERENCE APPLICATIONS 有权

    公开(公告)号：US20220075597A1

    公开(公告)日：2022-03-10

    申请号：US17017557

    申请日：2020-09-10

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Craig Warner ,  Eun Sub Lee ,  Sai Rahul Chalamalasetti ,  Martin Foltin

    IPC: G06F7/544 ,  G06F9/52 ,  G06F9/38 ,  G06N3/063 ,  G06F40/20

    Abstract: Systems and methods are provided for a multi-die dot-product engine (DPE) to provision large-scale machine learning inference applications. The multi-die DPE leverages a multi-chip architecture. For example, a multi-chip interface can include a plurality of DPE chips, where each DPE chip performs inference computations for performing deep learning operations. A hardware interface between a memory of a host computer and the plurality of DPE chips communicatively connects the plurality of DPE chips to the memory of the host computer system during an inference operation such that the deep learning operations are spanned across the plurality of DPE chips. Due to the multi-die architecture, multiple silicon devices are allowed to be used for inference, thereby enabling power-efficient inference for large-scale machine learning applications and complex deep neural networks. The multi-die DPE can be used to build a multi-device DNN inference system performing specific applications, such as object recognition, with high accuracy.

    UNIVERSAL INDUSTRIAL I/O INTERFACE BRIDGE
    46.
    发明申请
    UNIVERSAL INDUSTRIAL I/O INTERFACE BRIDGE 有权

    公开(公告)号：US20210390070A1

    公开(公告)日：2021-12-16

    申请号：US16903286

    申请日：2020-06-16

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Harvey Edward White, JR. ,  Aalap Tripathy ,  Martin Foltin ,  William Edward White

    IPC: G06F13/40 ,  G06F13/42

    Abstract: A universal industrial I/O interface bridge is provided. The universal industrial I/O interface bridge may be placed between a host and I/O interface cards to translate and manage electronic communications from these and other sources. Embodiments of the application may include (1) an improved hardware module, (2) an I/O discovery process to dynamically reprogram the universal industrial I/O interface bridge depending on the attached I/O card, (3) an abstraction process to illustrate the universal industrial I/O interface bridge and the physical I/O interfaces, (4) an alert plane within the universal industrial I/O interface bridge to respond to I/O alert pins, and (5) a secure distribution process for a firmware update of the universal industrial I/O interface bridge.

    Methods and systems for highly optimized memristor write process
    47.
    发明授权
    Methods and systems for highly optimized memristor write process 有权

    公开(公告)号：US11024379B2

    公开(公告)日：2021-06-01

    申请号：US16667773

    申请日：2019-10-29

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Amit Sharma ,  John Paul Strachan ,  Suhas Kumar ,  Catherine Graves ,  Martin Foltin ,  Craig Warner

    IPC: G11C11/00 ,  G11C13/00

    Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state. Thus, utility of memristors is enhanced by realizing an optimized write process with decrease latency and improved efficiency.

    SELF-HEALING DOT-PRODUCT ENGINE
    49.
    发明申请
    SELF-HEALING DOT-PRODUCT ENGINE 审中-公开

    公开(公告)号：US20200312406A1

    公开(公告)日：2020-10-01

    申请号：US16364717

    申请日：2019-03-26

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Amit S. Sharma ,  John Paul Strachan ,  Catherine Graves ,  Suhas Kumar ,  Craig Warner ,  Martin Foltin

    IPC: G11C13/00 ,  G06F11/10 ,  G11C29/52 ,  G06N3/04

    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

Patent Agency Ranking