中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

58 records (took 0.03 seconds)

    Phase-change random access memory
    41.
    发明授权
    Phase-change random access memory 有权
    相变随机存取存储器

    公开(公告)号：US07729160B2

    公开(公告)日：2010-06-01

    申请号：US11616969

    申请日：2006-12-28

    Applicant: Byung-Gil Choi ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hye-Jin Kim

    Inventor： Byung-Gil Choi ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hye-Jin Kim

    IPC: G11C11/00

    CPC classification number: G11C29/808 ,  G11C29/02 ,  G11C29/027 ,  G11C29/787 ,  G11C29/804 ,  G11C29/846

    Abstract: A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.

    Abstract translation: 相变随机存取存储器包括存储块，该存储块包括对应于同一列地址的多个存储器列并使用不同的输入/输出路径; 冗余存储器块，其包括使用不同的输入/输出路径的多个冗余存储器列; 以及输入/输出控制器，其使用所述多个冗余存储器列中的至少一个来修复所述多个存储器列中的至少一个，并且响应于输入/输出修复模式来控制使用冗余存储器列同时修复的存储器列的数量 控制信号。

    Input circuit of a non-volatile semiconductor memory device
    42.
    发明授权
    Input circuit of a non-volatile semiconductor memory device 有权
    非易失性半导体存储器件的输入电路

    公开(公告)号：US07710791B2

    公开(公告)日：2010-05-04

    申请号：US11984145

    申请日：2007-11-14

    Applicant: Kwang-jin Lee ,  Won-Seok Lee ,  Qi Wang ,  Hye-Jin Kim ,  Joon Yong Choi

    Inventor： Kwang-jin Lee ,  Won-Seok Lee ,  Qi Wang ,  Hye-Jin Kim ,  Joon Yong Choi

    IPC: G11C7/10 ,  G11C8/06 ,  G11C7/22 ,  G11C8/18

    CPC classification number: G11C7/1078 ,  G11C7/1084 ,  G11C7/225 ,  G11C16/10

    Abstract: A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or an electric fuse trim code, and that may generate a first buffered input signal; a column gate that may gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier that may amplify an output signal of the memory cell array to output to the column gate, and that may receive an output signal of the column gate to output to the memory cell array. The non-volatile semiconductor memory device may properly buffer an input signal of a small swing range.

    Abstract translation: 非易失性半导体存储器件可以包括可以包括多个存储晶体管的存储单元阵列; 输入电路，其可以响应于MRS修剪代码或电熔丝修剪代码来控制内部参考电压的电压电平和内部时钟信号的延迟时间，并且可以产生第一缓冲输入信号; 列门，其可以响应于解码列地址信号而选通第一缓冲输入信号; 以及读出放大器，其可以放大存储单元阵列的输出信号以输出到列门，并且可以接收列门的输出信号以输出到存储器单元阵列。 非易失性半导体存储器件可以适当地缓冲小摆动范围的输入信号。

    Nonvoltile memory device and method of driving the same
    43.
    发明申请
    Nonvoltile memory device and method of driving the same 有权
    非挥发性记忆装置及其驱动方法

    公开(公告)号：US20100080039A1

    公开(公告)日：2010-04-01

    申请号：US12585728

    申请日：2009-09-23

    Applicant: Byung-Gil Choi ,  Du-Eung Kim ,  Hye-Jin Kim

    Inventor： Byung-Gil Choi ,  Du-Eung Kim ,  Hye-Jin Kim

    IPC: G11C11/00 ,  G11C7/00 ,  G11C8/00 ,  G11C7/02

    CPC classification number: G11C13/0023 ,  G11C7/02 ,  G11C7/12 ,  G11C7/18 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026

    Abstract: A nonvolatile memory device and a method of driving the same are provided, which adopt an improved write operation. The method of driving a nonvolatile memory device includes providing the nonvolatile memory device including a plurality of memory banks each having a plurality of local bit lines and a plurality of variable resistance memory cells; selectively connecting read global bit lines for reading data with the local bit lines, and firstly discharging the selectively connected local bit lines by turning on local bit line discharge transistors coupled to the read global bit lines; and selectively connecting write global bit lines for writing data with the local bit lines, and secondly discharging the selectively connected local bit lines by turning on global bit line discharge transistors.

    Abstract translation: 提供一种非易失性存储器件及其驱动方法，其采用改进的写入操作。 驱动非易失性存储器件的方法包括提供包括多个存储体的非易失性存储器件，每个存储器组具有多个局部位线和多个可变电阻存储器单元; 选择性地连接读取全局位线用于与局部位线一起读取数据，并且首先通过连接耦合到读出的全局位线的局部位线放电晶体管来放电选择性连接的局部位线; 并选择性地连接用于将数据写入本地位线的写入全局位线，以及其次通过导通全局位线放电晶体管对选择连接的局部位线进行放电。

    Phase change memory device providing compensation for leakage current
    44.
    发明授权
    Phase change memory device providing compensation for leakage current 有权
    提供漏电流补偿的相变存储器件

    公开(公告)号：US07245526B2

    公开(公告)日：2007-07-17

    申请号：US11319266

    申请日：2005-12-29

    Applicant: Hyung-Rok Oh ,  Woo-Yeong Cho ,  Hye-Jin Kim

    Inventor： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Hye-Jin Kim

    IPC: G11C11/00

    CPC classification number: G11C13/004 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2213/79

    Abstract: A semiconductor memory device includes a plurality of phase change memory cells connected to the same bitline and different respective word lines. A read operation is performed on one of the memory cells by selecting the bitline and a corresponding wordline. While the read operation is performed, leakage current produced by non-selected memory cells is detected by a leakage detecting circuit and compensated by a leakage current supply circuit.

    Abstract translation: 半导体存储器件包括连接到同一位线和不同相应字线的多个相变存储器单元。 通过选择位线和相应的字线，对存储器单元之一执行读取操作。 在执行读取操作的同时，由漏电检测电路检测由未选择的存储单元产生的漏电流，并由泄漏电流供给电路进行补偿。

    Humidity sensor having anodic aluminum oxide layer, and fabricating method thereof
    46.
    发明授权
    Humidity sensor having anodic aluminum oxide layer, and fabricating method thereof 有权
    具有阳极氧化铝层的湿度传感器及其制造方法

    公开(公告)号：US08325460B2

    公开(公告)日：2012-12-04

    申请号：US12617848

    申请日：2009-11-13

    Applicant: Hyun-Chul Park ,  Hye-Jin Kim ,  Woon-Bong Hwang ,  Young-Deuk Kim ,  Kun-Hong Lee

    Inventor： Hyun-Chul Park ,  Hye-Jin Kim ,  Woon-Bong Hwang ,  Young-Deuk Kim ,  Kun-Hong Lee

    IPC: H01G5/012

    CPC classification number: G01N27/223

    Abstract: Disclosed are a humidity sensor and a fabricating method thereof. The humidity sensor includes a substrate, an anodic aluminum oxide layer formed on the substrate and having a plurality of holes, and electrodes formed on the anodic aluminum oxide layer, in order to improve sensitivity and accuracy of the humidity sensor. Further, the fabricating method of a humidity sensor includes preparing an aluminum substrate, forming an anodic aluminum oxide layer by oxidizing the aluminum substrate, and forming electrodes on the anodic aluminum oxide layer.

    Abstract translation: 公开了一种湿度传感器及其制造方法。 为了提高湿度传感器的灵敏度和精度，湿度传感器包括基板，形成在基板上并具有多个孔的阳极氧化铝层和形成在阳极氧化铝层上的电极。 此外，湿度传感器的制造方法包括制备铝基板，通过氧化铝基板形成阳极氧化铝层，以及在阳极氧化铝层上形成电极。

    NON-VOLATILE MEMORY DEVICE USING VARIABLE RESISTANCE ELEMENT WITH AN IMPROVED WRITE PERFORMANCE
    47.
    发明申请
    NON-VOLATILE MEMORY DEVICE USING VARIABLE RESISTANCE ELEMENT WITH AN IMPROVED WRITE PERFORMANCE 有权
    使用具有改进的写性能的可变电阻元件的非易失性存储器件

    公开(公告)号：US20120224437A1

    公开(公告)日：2012-09-06

    申请号：US13470617

    申请日：2012-05-14

    Applicant: Hye-Jin Kim ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Hung-Jun An

    Inventor： Hye-Jin Kim ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Hung-Jun An

    IPC: G11C5/14

    CPC classification number: G11C5/14 ,  G11C7/1078 ,  G11C7/1096 ,  G11C8/10 ,  G11C11/22 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2213/72

    Abstract: A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator configured to generate a first voltage, a voltage pad configured to receive an external voltage that has a level higher than the first voltage, a write driver configured to be supplied with the external voltage and configured to write data to the plurality of non-volatile memory cells selected from the memory cell array; a sense amplifier configured to be supplied with the external voltage and configured to read data from the plurality of non-volatile memory cells selected from the memory cell array, and a row decoder and a column decoder configured to select the plurality of non-volatile memory cells included in the memory cell array, the row decoder being supplied with the first voltage and the column decoder being supplied with the external voltage.

    Abstract translation: 提供了使用可变电阻元件的非易失性存储器件。 非易失性存储器件包括具有多个非易失性存储器单元的存储单元阵列，被配置为产生第一电压的第一电压发生器，被配置为接收具有高于第一电压的电平的外部电压的电压焊盘 写入驱动器，被配置为被提供有所述外部电压并被配置为向从所述存储单元阵列中选择的所述多个非易失性存储器单元写入数据; 感测放大器，被配置为被提供有外部电压并且被配置为从从存储单元阵列中选择的多个非易失性存储器单元读取数据;行解码器和列解码器，被配置为选择多个非易失性存储器 包括在存储单元阵列中的单元，行解码器被提供有第一电压，并且列解码器被提供有外部电压。

    Phase change memory devices and systems, and related programming methods
    49.
    发明授权
    Phase change memory devices and systems, and related programming methods 有权
    相变存储器件和系统以及相关编程方法

    公开(公告)号：US08116127B2

    公开(公告)日：2012-02-14

    申请号：US12559792

    申请日：2009-09-15

    Applicant: Woo-Yeong Cho ,  Kwang-Jin Lee ,  Hye-Jin Kim

    Inventor： Woo-Yeong Cho ,  Kwang-Jin Lee ,  Hye-Jin Kim

    IPC: G11C11/00

    CPC classification number: G11C8/10 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078

    Abstract: A method of writing data in a phase change memory includes receiving write data to be written to a selected phase change memory cell in the plurality of phase change memory cells, sensing data stored in the selected phase change memory cell, determining whether or not the sensed data is equal to the write data, and if the sensed data is not equal to the write data, iteratively applying a write current to the selected phase change memory cell, wherein a resistance state of the phase change memory cell is changed by heat corresponding to a level of the write current, and the level of the write current is changed between successive iterative applications.

    Abstract translation: 在相变存储器中写入数据的方法包括：接收要写入多个相变存储单元中的选定相变存储单元的写入数据，感测存储在所选择的相变存储单元中的数据，确定是否感测到 数据等于写入数据，并且如果感测到的数据不等于写入数据，则向所选择的相变存储器单元迭代地施加写入电流，其中相变存储单元的电阻状态由对应于 写入电流的电平和写入电流的电平在连续的迭代应用程序之间改变。

    Phase-change random access memory
    50.
    发明授权
    Phase-change random access memory 有权
    相变随机存取存储器

    公开(公告)号：US07961508B2

    公开(公告)日：2011-06-14

    申请号：US12771028

    申请日：2010-04-30

    Applicant: Byung-Gil Choi ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hye-Jin Kim

    Inventor： Byung-Gil Choi ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hye-Jin Kim

    IPC: G11C11/00

    CPC classification number: G11C29/808 ,  G11C29/02 ,  G11C29/027 ,  G11C29/787 ,  G11C29/804 ,  G11C29/846

    Abstract: A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.

    Abstract translation: 相变随机存取存储器包括存储块，该存储块包括对应于同一列地址的多个存储器列并使用不同的输入/输出路径; 冗余存储器块，其包括使用不同的输入/输出路径的多个冗余存储器列; 以及输入/输出控制器，其使用所述多个冗余存储器列中的至少一个来修复所述多个存储器列中的至少一个，并且响应于输入/输出修复模式来控制使用冗余存储器列同时修复的存储器列的数量 控制信号。

Patent Agency Ranking