公开(公告)号：US20160300920A1

公开(公告)日：2016-10-13

申请号：US15187971

申请日：2016-06-21

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Alexander Susiti ,  Markus Zundel ,  Reinhard Ploss

IPC: H01L29/49 ,  H01L21/283 ,  H01L21/265 ,  H01L29/423 ,  H01L29/861

CPC classification number: H01L29/7813 ,  H01L21/02123 ,  H01L21/02129 ,  H01L21/02321 ,  H01L21/26506 ,  H01L21/283 ,  H01L21/3115 ,  H01L21/31155 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/06 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device includes forming a trench in a semiconductor body at a first surface of the semiconductor body, forming a polysilicon material in the trench, introducing dopants into the polysilicon material by a high dose and low energy process, and performing a thermal treatment configured to drive-in the dopants into the polysilicon material.

Abstract translation: 一种制造半导体器件的方法包括在半导体本体的第一表面处形成半导体本体中的沟槽，在沟槽中形成多晶硅材料，通过高剂量和低能量过程将掺杂剂引入多晶硅材料中，并执行 配置成将掺杂剂驱入多晶硅材料的热处理。

公开(公告)号：US20160284795A1

公开(公告)日：2016-09-29

申请号：US15169290

申请日：2016-05-31

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Karl-Heinz Bach ,  Andrew Christopher Graeme Wood

IPC: H01L29/06 ,  H01L29/40 ,  H01L21/324 ,  H01L29/66 ,  H01L21/265 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/0634 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815

Abstract: What is provided is a field effect component including a semiconductor body, which extends in an edge zone from a rear side as far as a top side and which includes a semiconductor mesa, which extends in a vertical direction, which is perpendicular to the rear side and/or the top side. The semiconductor body in a vertical cross section further includes a drift region, which extends at least in the edge region as far as the top side and which is arranged partly in the semiconductor mesa, and a body region, which is arranged at least partly in the semiconductor mesa and which forms a pn junction with the drift region. The pn junction extends between two sidewalls of the semiconductor mesa.

公开(公告)号：US20160268422A1

公开(公告)日：2016-09-15

申请号：US15157645

申请日：2016-05-18

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Peter Brandl

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7815

Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate of a first conductivity type having a continuous first area and a second area, introducing dopants of the first conductivity type in the continuous first area of the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer, and forming trenches in the second semiconductor layer in the continuous first area.

Abstract translation: 一种制造半导体器件的方法包括在具有连续的第一区域和第二区域的第一导电类型的半导体衬底上形成第一半导体层，在第一半导体层的连续的第一区域中引入第一导电类型的掺杂剂， 在所述第一半导体层上形成第二半导体层，以及在所述连续的第一区域中在所述第二半导体层中形成沟槽。

公开(公告)号：US09431394B2

公开(公告)日：2016-08-30

申请号：US14013804

申请日：2013-08-29

Applicant: Infineon Technologies AG

Inventor： Markus Zundel

IPC: H01L23/31 ,  H01L23/00 ,  H01L27/088 ,  H01L23/495 ,  H01L29/78 ,  H01L29/739 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L27/088 ,  H01L23/3121 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7397 ,  H01L29/7813 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49175 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A power semiconductor package includes a housing, a semiconductor chip embedded in the housing, and at least four terminals partially embedded in the housing and partially exposed to the outside of the housing. The semiconductor chip includes a first doping region in ohmic contact with a first metal layer, a second doping region in ohmic contact with a second metal layer, and a plurality of first trenches that includes gate electrodes and first field electrodes electrically insulated from the gate electrodes. A first terminal of the four terminals is electrically connected to the first metal layer, a second terminal of the four terminals is electrically connected to the second metal layer, a third terminal of the four terminals is electrically connected to the gate electrodes of the first trenches, and a fourth terminal of the four terminals is electrically connected to the first field electrodes of the first trenches.

Abstract translation: 功率半导体封装包括壳体，嵌入壳体中的半导体芯片以及部分地嵌入壳体中并且部分地暴露于壳体外部的至少四个端子。 半导体芯片包括与第一金属层欧姆接触的第一掺杂区域，与第二金属层欧姆接触的第二掺杂区域和包括栅电极和与栅电极电绝缘的第一场电极的多个第一沟槽 。 四个端子的第一端子电连接到第一金属层，四个端子的第二端子电连接到第二金属层，四个端子的第三端子电连接到第一沟槽的栅极电极 并且四个端子的第四端子电连接到第一沟槽的第一场电极。

公开(公告)号：US20160197070A1

公开(公告)日：2016-07-07

申请号：US15051105

申请日：2016-02-23

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andreas Meiser ,  Hans-Peter Lang ,  Thorsten Meyer ,  Peter Irsigler

IPC: H01L27/06 ,  H01L29/45 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/861

CPC classification number: H01L29/7813 ,  H01L21/02 ,  H01L21/743 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/48 ,  H01L27/0629 ,  H01L27/0694 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7803 ,  H01L29/7827 ,  H01L29/7845 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor body having first and second opposing sides. Contact trenches extend, from the first and second sides, through a dielectric and into the semiconductor body. The contact trenches include conductive material electrically connected to the semiconductor body via sidewalls. The contact trenches include a first contact trench extending through a first dielectric and into the semiconductor body at the first side, the first contact trench including a first conductive material electrically connected to the semiconductor body adjoining the first contact trench, a second contact trench extending through a second dielectric and into the semiconductor body at the second side, the second contact trench including a second conductive material, a first contact pattern surrounded by the first dielectric at the first side, and a second contact pattern surrounded by the second dielectric at the second side.

Abstract translation: 半导体器件包括具有第一和第二相对侧的半导体本体。 接触沟槽从第一侧和第二侧延伸穿过电介质并进入半导体本体。 接触沟槽包括通过侧壁电连接到半导体本体的导电材料。 接触沟槽包括延伸穿过第一电介质并在第一侧进入半导体本体的第一接触沟槽，第一接触沟槽包括电连接到邻接第一接触沟槽的半导体本体的第一导电材料，延伸穿过第二接触沟槽 第二电介质并且在第二侧进入半导体本体，第二接触沟槽包括第二导电材料，由第一侧面处的第一电介质围绕的第一接触图案和在第二侧被第二电介质包围的第二接触图案 侧。

公开(公告)号：US09324829B2

公开(公告)日：2016-04-26

申请号：US13850037

申请日：2013-03-25

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Markus Zundel

IPC: H01L21/336 ,  H01L29/66 ,  H01L23/48 ,  H01L29/423 ,  H01L21/768 ,  H01L29/739 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/66477 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a trench extending from a first surface of a semiconductor body into the semiconductor body such that a first trench section and at least one second trench section adjoin the first trench section, wherein the first trench section is wider than the second trench section. A first electrode is formed, in the at least one second trench section, and dielectrically insulated from semiconductor regions of the semiconductor body by a first dielectric layer. An inter-electrode dielectric layer is formed, in the at least one second trench section, on the first electrode. A second electrode is formed, in the at least one second trench section on the inter-electrode dielectric layer, and in the first trench section, such that the second electrode at least in the first trench section is dielectrically insulated from the semiconductor body by a second dielectric layer.

Abstract translation: 一种方法包括形成从半导体主体的第一表面延伸到半导体本体中的沟槽，使得第一沟槽部分和与第一沟槽部分相邻的至少一个第二沟槽部分，其中第一沟槽部分比第二沟槽部分宽 。 第一电极在至少一个第二沟槽部分中形成，并且通过第一介电层与半导体本体的半导体区域介电绝缘。 在至少一个第二沟槽部分中，在第一电极上形成电极间电介质层。 第二电极形成在电极间电介质层的至少一个第二沟槽部分中，并且在第一沟槽部分中，使得至少在第一沟槽部分中的第二电极与半导体本体电介质绝缘 第二电介质层。

公开(公告)号：US09218958B2

公开(公告)日：2015-12-22

申请号：US14102107

申请日：2013-12-10

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Markus Zundel ,  Anton Mauder ,  Andreas Meiser ,  Franz Hirler ,  Hans Weber

IPC: H01L21/425 ,  H01L21/02 ,  H01L21/265 ,  H01L21/321

CPC classification number: H01L21/02258 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02299 ,  H01L21/02345 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/32105 ,  H01L29/66325 ,  H01L29/66477

Abstract: A method for forming a semiconductor device includes carrying out an anodic oxidation of a surface region of a semiconductor substrate to form an oxide layer at a surface of the semiconductor substrate by generating an attracting electrical field between the semiconductor substrate and an external electrode within an electrolyte to attract oxidizing ions of the electrolyte, causing an oxidation of the surface region of the semiconductor substrate. Further, the method includes reducing the number of remaining oxidizing ions within the oxide layer, while the semiconductor substrate is within an electrolyte.

Abstract translation: 一种形成半导体器件的方法包括：通过在半导体衬底和半导体衬底内的外部电极之间产生吸引电场，在半导体衬底的表面上进行半导体衬底的表面区域的阳极氧化以形成氧化物层 以吸引电解质的氧化离子，引起半导体衬底的表面区域的氧化。 此外，该方法包括减少氧化物层内剩余氧化离子的数量，同时半导体衬底在电解质内。

公开(公告)号：US20150346270A1

公开(公告)日：2015-12-03

申请号：US14754738

申请日：2015-06-30

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Franz Hirler ,  Peter Nelle

IPC: G01R31/26

CPC classification number: G01R31/2601 ,  G01R31/2884 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.

Abstract translation: 根据一个或多个实施例的测试方法可以包括：提供待测试的半导体器件，所述半导体器件包括至少一个器件单元，所述至少一个器件单元具有至少一个沟槽，至少一个第一端子电极区域 以及至少一个第二端子电极区域，至少一个栅极电极和至少部分地设置在所述至少一个沟槽中的至少一个附加电极，其中所述至少一个附加电极的电势可以与电势分开地控制 所述至少一个第一端子电极区域，所述至少一个第二端子电极区域和所述至少一个栅极电极; 以及向至少一个附加电极施加至少一个电测试电位以检测所述至少一个器件单元中的缺陷。

公开(公告)号：US20150333058A1

公开(公告)日：2015-11-19

申请号：US14813738

申请日：2015-07-30

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Markus Zundel ,  Till Schloesser

IPC: H01L27/08 ,  H01L21/768 ,  H01L29/40 ,  H01L49/02

CPC classification number: H01L27/0805 ,  H01L21/7687 ,  H01L21/76877 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L28/90 ,  H01L29/407

Abstract: A semiconductor device in a semiconductor substrate includes a trench in a first main surface of the semiconductor substrate. The trench includes a first trench portion extending in a first direction and a second trench portion extending in the first direction. The first trench portion is connected with the second trench portion in a lateral direction. The first trench portion and the second trench portion are arranged one after the other along the first direction. The semiconductor device further includes a trench conductive structure having a conductive material disposed in the first trench portion, and a trench capacitor structure having a capacitor dielectric and a first capacitor electrode disposed in the second trench portion. The first capacitor electrode includes a layer lining a sidewall of the second trench portion.

Abstract translation: 半导体衬底中的半导体器件包括在半导体衬底的第一主表面中的沟槽。 沟槽包括沿第一方向延伸的第一沟槽部分和沿第一方向延伸的第二沟槽部分。 第一沟槽部分沿横向方向与第二沟槽部分连接。 第一沟槽部分和第二沟槽部分沿着第一方向一个接一个布置。 半导体器件还包括具有设置在第一沟槽部分中的导电材料的沟槽导电结构，以及具有电容器电介质的沟槽电容器结构和设置在第二沟槽部分中的第一电容器电极。 第一电容器电极包括衬在第二沟槽部分的侧壁上的层。

公开(公告)号：US20150311294A1

公开(公告)日：2015-10-29

申请号：US14712178

申请日：2015-05-14

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Markus Zundel

IPC: H01L29/40 ,  H01L21/28 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/7813 ,  H01L21/28008 ,  H01L21/28229 ,  H01L21/743 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of producing a controllable semiconductor component includes providing a semiconductor body with a top side and a bottom side, and forming a first trench protruding from the top side into the semiconductor body and a second trench protruding from the top side into the semiconductor body. The first trench has a first width and a first depth, and the second trench has a second width greater than the first width and a second depth greater than the first depth. The method further includes forming, in a common process, an oxide layer in the first trench and in the second trench such that the oxide layer fills the first trench and electrically insulates a surface of the second trench, and removing the oxide layer from the first trench completely or at least partly such that the semiconductor body comprises an exposed first surface area arranged in the first trench.

Abstract translation: 一种制造可控半导体部件的方法包括提供具有顶侧和底侧的半导体本体，以及形成从顶侧突出到半导体本体的第一沟槽和从顶侧突出到半导体本体中的第二沟槽。 第一沟槽具有第一宽度和第一深度，并且第二沟槽具有大于第一宽度的第二宽度和大于第一深度的第二深度。 该方法还包括在公共工艺中形成第一沟槽和第二沟槽中的氧化物层，使得氧化物层填充第一沟槽并使第二沟槽的表面电绝缘，并且从第一沟槽中去除氧化物层 沟槽完全或至少部分地使得半导体主体包括布置在第一沟槽中的暴露的第一表面区域。