公开(公告)号：US20190206823A1

公开(公告)日：2019-07-04

申请号：US15857332

申请日：2017-12-28

Applicant: INTEL CORPORATION

Inventor： Kristof Darmawikarta ,  Sri Ranga Sai Boyapati ,  Hiroki Tanaka ,  Robert A. May

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L24/19 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/20

Abstract: An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.

公开(公告)号：US20190198447A1

公开(公告)日：2019-06-27

申请号：US16329644

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Kristof Darmawikarta ,  Robert A. May ,  Sri Ranga Sai Boyapati

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L25/18

Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

公开(公告)号：US10121679B1

公开(公告)日：2018-11-06

申请号：US15721384

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Kristof Darmawikarta ,  Arnab Sarkar ,  Hiroki Tanaka ,  Robert A. May ,  Sri Ranga Sai Boyapati

IPC: H01L23/532 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments of the present disclosure may relate to a package substrate that may include a layer having a layer surface that is planarized and a via within the layer, where the via includes a via surface that is exposed on the layer surface, and where the via surface is planarized. The package substrate may further include a bond pad on the layer surface, where a first thickness of the bond pad includes a seed layer on the via surface, and where a second thickness of the bond pad includes a plating stack on the seed layer. Other embodiments may be described or claimed.