公开(公告)号：US09846962B2

公开(公告)日：2017-12-19

申请号：US14865200

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kalyan K. Bhiravabhatla ,  Subramaniam M. Maiyuran ,  Saurabh Sharma

IPC: G06T15/30 ,  G06T15/80 ,  G06T11/40 ,  G06T15/00

CPC classification number: G06T15/30 ,  G06T11/40 ,  G06T15/005 ,  G06T15/80

Abstract: Marking “Clipped Triangles” as visible triangles for all tiles may be avoided by instead finding an approximate clipping area and marking the triangles as visible only in those tiles in the Position Only Shading Pipe (POSH) pipe. This avoids rendering the triangle in the replay pipe in those tiles where it may not be visible.

公开(公告)号：US09824412B2

公开(公告)日：2017-11-21

申请号：US14494653

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Saurabh Sharma ,  Subramaniam Maiyuran ,  Thomas A. Piazza ,  Kalyan K. Bhiravabhatla ,  Peter L. Doyle ,  Paul A. Johnson ,  Bimal Poddar ,  Jon N. Hasselgren ,  Carl J. Munkberg ,  Tomas G. Akenine-Moller ,  Harri Syrja ,  Kevin Rogovin ,  Robert L. Farrell

IPC: G06T15/40 ,  G06T1/20 ,  G06T15/50 ,  G09G5/393

CPC classification number: G06T1/20 ,  G06T15/40 ,  G06T15/405 ,  G06T15/503 ,  G09G5/393

Abstract: In position-only shading, two geometry pipes exist, a trimmed down version called the Cull Pipe and a full version called the Replay Pipe. Thus, the Cull Pipe executes the position shaders in parallel with the main application, but typically generates the critical results much faster as it fetches and shades only the position attribute of the vertices and avoids the rasterization as well as the rendering of pixels for the frame buffer. Furthermore, the Cull Pipe uses these critical results to compute visibility information for all the triangles whether they are culled or not. On the other hand, the Replay Pipe consumes the visibility information to skip the culled triangles and shades only the visible triangles that are finally passed to the rasterization phase. Together the two pipes can hide the long cull runs of discarded triangles and can complete the work faster in some embodiments.

公开(公告)号：US20220148261A1

公开(公告)日：2022-05-12

申请号：US17526462

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： Justin DeCell ,  Saurabh Sharma ,  Subramaniam Maiyuran ,  Raghavendra Miyar ,  Jorge Garcia Pabon

IPC: G06T17/10 ,  G06T17/20 ,  G06T1/20 ,  G06T15/00

Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.

公开(公告)号：US11250539B2

公开(公告)日：2022-02-15

申请号：US16930935

申请日：2020-07-16

Applicant: Intel Corporation

Inventor： Vasanth Ranganathan ,  Saikat Mandal ,  Karol A. Szerszen ,  Saurabh Sharma ,  Vamsee Vardhan Chivukula ,  Abhishek R. Appu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Altug Koker

IPC: G09G5/00 ,  G06T1/60 ,  G06F12/0875 ,  G06T1/20

Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.

公开(公告)号：US20210149716A1

公开(公告)日：2021-05-20

申请号：US16684077

申请日：2019-11-14

Applicant: Intel Corporation

Inventor： Justin DeCell ,  Saurabh Sharma

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0802

Abstract: Systems and methods for scheduling thread order to improve cache efficiency are disclosed. In one embodiment, a graphics processor includes processing resources and schedule and dispatch logic to schedule and dispatch threads to the processing resources. The schedule and dispatch logic is configured to receive threads, to schedule and dispatch the threads based on a forward thread dispatch having a forward thread order, and to determine whether to disable a reversing of a thread order upon completion of at least a portion of the forward thread dispatch including a completion or ending of a draw call or a dispatch.

公开(公告)号：US10916052B2

公开(公告)日：2021-02-09

申请号：US16395717

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Justin DeCell ,  Saurabh Sharma ,  Subramaniam Maiyuran ,  Raghavendra Miyar ,  Jorge Garcia Pabon

IPC: G06T17/10 ,  G06T17/20 ,  G06T1/20 ,  G06T15/00

Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.

公开(公告)号：US10262388B2

公开(公告)日：2019-04-16

申请号：US15483236

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Saurabh Sharma ,  Abhishek Venkatesh ,  Travis T. Schluessler ,  Prasoonkumar Surti ,  Altug Koker ,  Aravindh V. Anantaraman ,  Pattabhiraman P. K. ,  Abhishek R. Appu ,  Joydeep Ray ,  Kamal Sinha ,  Vasanth Ranganathan ,  Bhushan M. Borole ,  Wenyin Fu ,  Eric J. Hoekstra ,  Linda L. Hurd

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

公开(公告)号：US10102609B1

公开(公告)日：2018-10-16

申请号：US15477039

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Vasanth Ranganathan ,  Saikat Mandal ,  Karol A. Szerszen ,  Saurabh Sharma ,  Vamsee Vardhan Chivukula ,  Abhishek R. Appu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Altug Koker

IPC: G06T15/40 ,  G06T1/60 ,  G06T1/20 ,  G06F12/0875

Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.

公开(公告)号：US20170091985A1

公开(公告)日：2017-03-30

申请号：US14865200

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kalyan K. Bhiravabhatla ,  Subramaniam M. Maiyuran ,  Saurabh Sharma

IPC: G06T15/30 ,  G06T15/80 ,  G06T15/08

CPC classification number: G06T15/30 ,  G06T11/40 ,  G06T15/005 ,  G06T15/80

Abstract: Marking “Clipped Triangles” as visible triangles for all tiles may be avoided by instead finding an approximate clipping area and marking the triangles as visible only in those tiles in the posh pipe. This avoids rendering the triangle in the replay pipe in those tiles where it may not be visible.